# Flip - flops. We begin our study of such circuits be discussing the elements necessary to implement the “storage” portion of sequential systems. I present.

## Presentation on theme: "Flip - flops. We begin our study of such circuits be discussing the elements necessary to implement the “storage” portion of sequential systems. I present."— Presentation transcript:

Flip - flops

We begin our study of such circuits be discussing the elements necessary to implement the “storage” portion of sequential systems. I present a simple combinational circuit that will store events (binary signals) that have occurred in the past. R (reset) S (set) Q is the inverse of Q. In order to examine the TT for this circuit we must consider both the inputs (R, S) and the state (or conditions) present at Q (and Q). QQQQ

stateSRQQ’ 0011not permitted (undefined) 10110 21001 11depends on prior state of Q, Q’ In short, this circuit “remembers” the last input (S or R) to have been at logical 0. (The input conditions S=1, R=1 leaves the component in either states 1 or 2, whichever occurred last.) We convert this element - know called an RS (or Set-Reset) flip-flop (FF) - into a single block that we can use repeatedly in our designs (without having to redraw the individual gates).

S Q R Q’ The inverters (circles) on the inputs remind us that we need a logical 0 on these inputs to force the corresponding outputs to become logical 1. It is very important to remember that both inputs should not be 0 at the same time or the circuit will become confused.

How do you implement an RS FF that remembers the last input that was logical 1 rather than logical 0? (Hint: use NOR gates; I will let you draw the diagram). We now introduce an RS FF that has a new feature, namely a (logical) signal that controls when (i.e., the time at which) the inputs are allowed to pass to the FF to set (or reset) their state. This is done by adding two gates that will block the inputs (R and S) unless the control lets them pass through. This is called an SR Latch FF. QQQQ RSRS C X X RS FF

How does this work? (Pretty good.) While C = 0, nothing can get through the gates marked “X” because the outputs of these gates will be 1 no matter what the logical levels on the other inputs. Therefore the “old” (core) SR FF will not change its state as we have already discussed. When C = 1, the (X) gates response is governed by the S and R inputs which are allowed to pass to the RS FF. The outputs are then governed by the normal TT (state) values of an RS FF. The (control) signal C is also referred to as a “clock.” It will often have the following shape as a function of time. ignore RS inputs Follow the RS inputs 0 1

We don’t actually need both S and R as separate signals. I can simply invert a common “data” input (named D) to obtain the inverse. In such circumstances we will never run into the “illegal” state because “S” and “R” will always have inverse logical values. This produces a FF called the D Latch. QQQQ D C RS FF

Basic Storage Building Elements There are three general categories of basic storage element: Latch – as long as the control signal remains active, any changes in the data will be reflected in changes in the output state of the component. (Frequently a sub- element of more complex FFs.) FF – the data inputs of a FF are derived in part from the outputs of the same FF. Edge-triggered – triggers only during a transition of the control signal (clock). We have already considered the latch. We next discuss the Master-Slave FF concept. As shown below this can employ two latches in a way that tightly controls when the FF changes state thereby minimizing errors that may be introduced by noise or other artifacts.

Exploring one form of edge-triggered FF: SCRSCR DCDC DCDC QQQQ The clock signal looks like: FF1FF2

The sequence can be examined as follows: clock FF1 FF2 Result 0 enabled disabled FF1 follows the data input (D). 1 disabled enabled FF1 transfer its state to FF2. FF1 does not follow D. At the instant that the clock makes its positive transition data that was being tracked (in FF1) is transferred to FF2 while at the same time tracking ceases. This is shown as a dotted path in the diagram above. Why is this second inverter present? It does not serve any logical purpose because double inversion simply cancels any logical effect, so why is it included????

Dealing with the “illegal” imput conditions of the latch – the inputs that result in “undecided” states. What shall we do? Contending with undefined states: If both inputs are in the undefined state, we cause the FF to change its (output) state. If Q was 1 before, it changes to 0 and vice versa. The resultant architecture is the “Master-Slave JK FF”. SCRSCR SCRSCR QQQQ JCKJCK

FF2 FF1 AB Clock or control signal QQQQ Data path (e.g., inputs) Q and Q are the outputs of the FF. They are always the inverse of each other. The Master-Slave FF concept

The State Table describes how this MSJKFF changes in response to various input conditions: Before a clockAfter a clock JKQQ 0000 0011 0100 0110 1001 1011 1101 1110 Notice that when both (JK) inputs are low the FF does not change state for clock “ticks.” When both (JK) inputs are high the FF will invert (change) its state after a tick.

The clock signal is essential in order to analyze the MSJKFF. The leading edge of the clock; transfer data to the first FF. The trailing edge of the clock; disable input FF; transfer data from first to second FF. The clock sequence shown above is referred to as a “click” (because if such a signal is applied to a speaker you would hear a “click”).

Download ppt "Flip - flops. We begin our study of such circuits be discussing the elements necessary to implement the “storage” portion of sequential systems. I present."

Similar presentations