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1 Sequential Circuits Registers and Counters. 2 Master Slave Flip Flops.

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Presentation on theme: "1 Sequential Circuits Registers and Counters. 2 Master Slave Flip Flops."— Presentation transcript:

1 1 Sequential Circuits Registers and Counters

2 2 Master Slave Flip Flops

3 Types of Sequential Circuits Two types of sequential circuits: Synchronous: The behavior of the circuit depends on the input signal at discrete instances of time (also called clocked) Asynchronous: The behavior of the circuit depends on the input signals at any instance of time and the order of the inputs change 3

4 Master-Slave Flip-Flop The rising edge of the clock loads new data into the master, while the slave continues to hold previous data. The falling edge of the clock loads the new master data into the slave. 4 At C = 1, Master is Enabled and Slave is disabled C = 0, Slave is enabled and Master is disabled Y Q y C C Q MasterSlave

5 5 Registers

6 Registers Several flip-flops grouped together with a common clock to form a register. Each flip-flop can store one bit of information, A register with n flip-flops can store/load n bits of information (e.g. to store data in the CPU) OR to transferring data between registers is a common operation in digital systems Shift Register: A register that allows each of the flip -flops to pass the stored information to its adjacent neighbour Some of shift registers are: Parallel In parallel out (PIPO) Serial In Serial Out register (SISO) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) 6

7 4-bit register 4-bit register - (PIPO) 7 The common clock input triggers all flip flops on the positive edge of each pulse, and the binary data available at the four inputs are transferred into the register (Loading/ up loading). The four outputs can be sampled at any time to obtain the binary Information stored in the register.

8 4-bit register (SISO) / Shift register 8 The bits will arrive in serial - one bit at a time The Input is applied to first flip-flop and shifted along one at each clock event

9 Figure 2.2 illustrates entry of the four bits 1010 into the register. Figure 2.3 shows the four bits (1010) being serially shifted out of the register and replaced by all zeros. 9

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12 SIPO Register 12 RESET is an input to CLEAR the FF One application of shift registers is converting between “serial data” and “parallel data” Accepts data serially. Outputs of all stages are available simultaneously

13 PISO Register PISO Register 13 Bits are load simultaneously, but output is Shifted serially.

14 14 Counters

15 Counters A counter is essentially a register that goes though a predetermined sequence of binary states. It counts in binary from 0 to 2ⁿ-1, where n is the number of FFs The output value increases by one on each clock cycle After the largest value, the output “wraps around” back to 0 Counters can act as simple clocks to keep track of “time”. They also used to record how many times something has happened or how many steps have been performed in some computation? All processors in the computers contain a Program Counter, or PC to keep track of the instruction currently being executed and after each clock cycle the next instruction will be executed. 15

16 Classification of counters:  Asynchronous (ripple) counter Up and Down counter  Synchronous counter 16

17  Only the first flip-flop is clocked by an external clock. All subsequent flip- flops are clocked by the output of the preceding flip-flop.  It is called ripple-counters because of the way the clock pulse ripples it way through the flip-flops  They also known by Frequency Division (to lower the hertz) 17 Asynchronous (ripple) counter

18 18 FF0 changes state at the rising edge of each clock pulse, but FF1 changes only when triggered by the rising edge of the (complement of Q signal) output of FF0 (positive edge –triggering) Asynchronous Up counter Timing diagram 0 0 0 1 0 0

19 Down counter Down counter To convert the above Up Counter to Down counter change the ripple of the clock to be taken from Q of FF0 to trigger FF1 instead of and so on 19

20 Synchronous Counters All flip-flops are clocked simultaneously by an external clock. Synchronous counters are an example of state machine design because they have a set of states and a set of transition rules for moving between those states after each clocked event 20 complement No change complement No change complement

21 Random Access Memory (RAM) 21  Stores binary information in groups of bits called words.  The data consists of n lines (for n-bit words). Data input lines provide the information to be stored (written) into the memory, while data output lines carry the information out (read) from the memory.  The address consists of k lines which specify which word (among the 2 k words available) to be selected for reading or writing.  The control lines Read and Write (usually combined into a single control line ) specifies the direction of transfer of the data.  Static RAMs use flip-flops as the memory cells

22 22 The control lines Read and Write (usually combined into a single control line ) specifies the direction of transfer of the data

23 H.W The submission has to be by the end of this week H.W The submission has to be by the end of this week Write your full name and the group number on the answer sheet 1- Draw the state diagram of T Flip Flop 2- From the below block diagram of a counter : a) What kind of triggering is used? b)With the aid of timing diagram clarify the sequence of the main states Qs that is possible by this counter assuming their initial states are 0 c)What is the new result if we replace the JK flip flop with the T flip flop in this counter and why? 23

24 H.W H.W 3- From the following logic circuit draw the timing diagram for ‘Q’. Assume ‘Q’ has an initial value of ‘0’ 24

25 4- From this circuit find out the boolean expression of the next states of each Flip flop and the output of the circuit (Y), then complete its excitation Table. 5- Write at least 4 pages to highlight the basics definitions and operation of RAM 25

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