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CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic A: Flip-Flops José Nelson Amaral.

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Presentation on theme: "CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic A: Flip-Flops José Nelson Amaral."— Presentation transcript:

1 CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic A: Flip-Flops José Nelson Amaral

2 CMPUT Computer Organization and Architecture II2 Reading Assignment Chapter 7 (sections 7.1, 7.2)

3 CMPUT Computer Organization and Architecture II3 Gate Delays and Time Diagrams XX’ Time X X’ 11 22

4 CMPUT Computer Organization and Architecture II4 Oscillating Circuit X Time X

5 CMPUT Computer Organization and Architecture II5 Oscillating Circuit X Y What are the values of X and Y in this circuit?

6 CMPUT Computer Organization and Architecture II6 Bistable element zThe simplest sequential circuit zTwo states yOne state variable, say, Q LOWHIGH LOW

7 CMPUT Computer Organization and Architecture II7 Analog analysis yAssume pure CMOS thresholds, 5V rail yTheoretical threshold center is 2.5 V

8 CMPUT Computer Organization and Architecture II8 Metastability zMetastability is inherent in any bistable circuit zTwo stable points, one metastable point

9 CMPUT Computer Organization and Architecture II9 Analog analysis zAssume pure CMOS thresholds, 5V rail zTheoretical threshold center is 2.5 V 2.5 V

10 CMPUT Computer Organization and Architecture II10 Analog analysis zAssume pure CMOS thresholds, 5V rail zTheoretical threshold center is 2.5 V 2.5 V 2.0 V 4.8 V 2.5 V2.51 V4.8 V0.0 V 5.0 V

11 CMPUT Computer Organization and Architecture II11 Another look at metastability

12 CMPUT Computer Organization and Architecture II12 Why all the harping on metastability? yAll real systems are subject to it xProblems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times. ySevere in high-speed systems since clock periods are so short, “metastability resolution time” can be longer than one clock period. yMany digital designers, products, and companies have been burned by this phenomenom.

13 CMPUT Computer Organization and Architecture II13 Back to the bistable…. zHow to control it? yControl inputs zS-R latch

14 CMPUT Computer Organization and Architecture II14 The Set-Reset Latch P Q S R If S=0 and R=0, what are the stable states for this circuit? (i) Assume P=0; P=0 and Q=1 is stable 1

15 CMPUT Computer Organization and Architecture II15 The Set-Reset Latch P Q S R If S=0 and R=0, what are the stable states for this circuit? (i) Assume P=0; (ii) Assume P=1; P=0 and Q=1 is stable 0 P=1 and Q=0 is stable

16 CMPUT Computer Organization and Architecture II16 The Set-Reset Latch P Q S R If the state is P=1 and Q=0, and the input S changes to 1, what happens? The new stable state is P=0 and Q=1 What happens if S changes to zero now? 0 The state does not change!

17 CMPUT Computer Organization and Architecture II17 The Set-Reset Latch P Q S R If the state is P=0 and Q=1, and the input R is changed to 1, what happens? The new stable state is P=1 and Q=0 What happens if S changes to zero now? 0 The state does not change!

18 CMPUT Computer Organization and Architecture II18 The Set-Reset Latch Therefore: - if S changes to 1 for a short period of time, the flip-flop goes to the state P=0, Q=1; - if R changes to 1 for a short period of time, the flip-flop goes to the state P=1, Q=0; We consider Q to be the output of the latch, therefore S is the “Set” input, and R is the “Reset” input. What happens if R and S are 1 at the same time?

19 CMPUT Computer Organization and Architecture II19 The Set-Reset Latch P Q S R Lets assume that P=0, Q=1 initially and then R and S become The new stable state is P=0 and Q=0 But this is no longer a latch because P is no longer a complement of Q! S=1 and R=1 is not allowed.

20 CMPUT Computer Organization and Architecture II20 The Set-Reset Latch Q S R Q’ Q R S FF

21 CMPUT Computer Organization and Architecture II21 The Set-Reset Latch Q Q’ R S FF S(t) R(t) Q(t) 111 XX Q(t+  ) = S(t) + Q(t)R’(t)

22 CMPUT Computer Organization and Architecture II22 S-R latch operation Metastability is possible if S and R are negated simultaneously.

23 CMPUT Computer Organization and Architecture II23 S-R latch timing parameters zPropagation delay zMinimum pulse width

24 CMPUT Computer Organization and Architecture II24 S-R latch symbols

25 CMPUT Computer Organization and Architecture II25 S-R latch using NAND gates

26 CMPUT Computer Organization and Architecture II26 S-R latch with enable

27 CMPUT Computer Organization and Architecture II27 Using an enable S-R latch to build a Trigger Latch T   Q T S’ R’’ S’ R’ FF Q Q’ T What happens if the T input is at 1 for a longer time? The flip-flop oscillates until T goes back to 0.

28 CMPUT Computer Organization and Architecture II28 D latch

29 CMPUT Computer Organization and Architecture II29 D-latch operation

30 CMPUT Computer Organization and Architecture II30 D-latch timing parameters zPropagation delay (from C or D) zSetup time (D before C edge) zHold time (D after C edge)

31 CMPUT Computer Organization and Architecture II31 Edge-triggered D flip-flop behavior

32 CMPUT Computer Organization and Architecture II32 Edge-triggered D flip-flop behavior

33 CMPUT Computer Organization and Architecture II33 D flip-flop timing parameters zPropagation delay (from CLK) zSetup time (D before CLK) zHold time (D after CLK)

34 CMPUT Computer Organization and Architecture II34 Other D flip-flop variations zNegative-edge triggered zClock enable

35 CMPUT Computer Organization and Architecture II35 J-K flip-flops


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