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CMOS Transistors

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Outline Qualitative Description of CMOS Transistor g m /I D Design Biasing a transistor Using g m /I D Approach Design Using Cadence

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A Crude Metal Oxide Semiconductor (MOS) Device P-Type Silicon is slightly conductive. Positive charge attract negative charges to interface between insulator and silicon. A conductive path is created If the density of electrons is sufficiently high. Q=CV. V2 causes movement of negative charges, thus current. V1 can control the resistivity of the channel. The gate draws no current!

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An Improved MOS Transistor n+ diffusion allows electrons move through silicon. (provide electrons)(drain electrons)

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Typical Dimensions of MOSFETs These diode must be reversed biased. tox is made really thin to increase C, therefore, create a strong control of Q by V.

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A Closer Look at the Channel Formulation Need to tie substrate to GND to avoid current through PN diode. Positive charges repel the holes creating a depletion region, a region free of holes. Free electrons appear at VG=VTH. VTH=300mV to 500 mV (OFF)(ON)

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Channel Resistance As VG increases, the density of electrons increases, the value of channel resistance changes with gate voltage.

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Drain Current as a function of Drain Voltage Resistance determined by VG.

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Drain Current as a function of Gate Voltage Higher VG leads to a lower channel resistance, therefore larger slope.

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Length Dependence The resistance of a conductor is proportional to the length.

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Dependence on Oxide Thickness Q=CV C is inversely proportional to 1/tox. Lower Q implies higher channel resitsance.

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Width Dependence The resistance of a conductor is inversely proportional to the cross section area. A larger device also has a larger capacitance!

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Channel Pinch Off Q=CV – V=VG-V OXIDE-Silicon V OXIDE-Silicon can change along the channel! Low V OXIDE-Silicon implies less Q.

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VG-VD is sufficiently large to produce a channel VG-VD is NOT sufficiently large to produce a channel No channel Electrons are swept by E to drain. Drain can no longer affect the drain current!

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Regions No channel (No Dependence on VDS)

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Determination of Region How do you know whether a transistor is in the linear region or saturation region? – If VDS>(VGS-VTH) and VGS>VTH, then the device is in the saturation region. – If VDS VTH, then the device is in the linear region.

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Graphical Illustration

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Limited VDS Dependence During Saturation As VDS increase, effective L decreases, therefore, ID increases.

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Pronounced Channel Length Modulation in small L

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Transconductance As a voltage-controlled current source, a MOS transistor can be characterized by its transconductance: It is important to know that

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What Happens to g m /I D when W and I D are doubled ?

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Body Effect The threshold voltage will change when VSB=0!

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Experimental Data of Body Effect The threshold voltage will increase when VSB increases.

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Small Signal Model for NMOS Transistor

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PMOS Transistor

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IV Characteristics of a PMOS

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Small Signal Model of PMOS

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Small Signal Model of NMOS

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g m /I D Design Approach

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g m /I D Design Flow Specs Design Equations (Analytical ) g m /I d Data Set (Emprical) g m /I D Design Optimization W/L Ratios (F. Silveira, JSSC, 1996.)

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Intuition g m g ds g m /I D g m /g ds 2g m 2g ds g m /I D g m /g ds 2g m 2g ds g m /I D g m /g ds

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g m /I D Data Set g m /g ds g m /g mbs I D /W C gd /C gg C gs /C gg ….more (F. Silveira, JSSC, 1996.)

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Design Example

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Calculation (gm is determined) Initially assume that g m r o is large!

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gm/gds (50)

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Current Density

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Biasing an MOS Transistor Using g m /I D technique Section 7.1 J.Ou Sonoma State Univeristy

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Basic Analysis Use 1.2 V (Modified Ex 7.1)

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Design Equations

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Assumption: VDD=1.2 V Transistor Information: Type: 120 nm Specify VDS Note var1_1 is ‘vsd’ if pmos is used Note var2_1 is ‘vns’ if nmos is used. In this example, is initially unknown, so we will assume that it is 0.0

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Interpolation Since the database base can not be so large as to keep all possible values of vds/vsb, we have to interpolate based on existing values, which are available On 0.1 V interval. Current release: need to enter inBias <= the minVar1 and maxVar1. minVar=maxVar-0.1

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Browse Database dBrowse2D(25, 'pfet', '15.0u', 'vsd', 0.3, 0.4, 0.353, 'vns', 0.5, 0.6, 0.577, 'vth') Variable name=dBrowse2D(gmoverid, type, length, var1, minVar1, maxVar1,inBias1, var2, minVar2, maxVar2,inBias2, ‘parameter’ ) Valid parameters: gmovergds, gmovergmbs, vth, ft, gmoveridft, idoverw, vod, region, fndbderiv cgdovercgg,cddovercgg, cgsovercgg, csbovercgg, cdbovercgg, ron, vdsat, rseff, rdeff type: nfet, pfet length: {'120n' '180n' '250n' '350n' '600n' '800n' '1.0u' '2.0u' '3.0u' '4.0u' '5.0u' '6.0u' '7.0u' '8.0u' '9.0u' '10.0u' '15.0u' '20.0u'} (text string)

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Iteration Start with – length=‘120nm’ – gmoverid=20 – VDS=VDD/2, VSB=0 Calculate – vod_1 – vth_ – vgs_1 – vx (gate voltage) – vs (source voltage) – ID – Idoverw – W – RD – Vd – Vds=Vd-Vs

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Iteration Example

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Design Iterations Iteratio n VSIDSWRDVds 00.1 V392uA53.06 um 1.529K ohms V uA45.16 um 1.89 Kohms V uA um Kohms uA Kohms 0.265

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Matlab & Simulation ParametersMatlabCadence W46.56 um46 um Vx0.857 V ids336.8 uA339 uA gm6.7 mS6.80 mS gm/ids Vs0.336 V0.339 V Vd0.6 V0.593 V Vds0.263 V0.257V Vth0.5 V0.497 V

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Circuit Design Using Cadence J.Ou

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Start Cadence

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Create New Cellview

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Add Instance

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Add a Resistor

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Add Ground

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Add Power

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Add Wire

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Done!

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Start ADE L

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Start DC Analysis

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Netlist and Run

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Annotate DC Node Voltages

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Model Library Setup

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DC Voltage Annotated

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Component Display

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Display DC Operating Point Click on the device to display values!

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Save State

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