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(Neil weste p:- 41- 91).  A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain.

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Presentation on theme: "(Neil weste p:- 41- 91).  A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain."— Presentation transcript:

1 (Neil weste p: )

2  A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the gate.

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4 n-channel enhancement n-channel depletion p-channel enhancement n-channel depletion I ds V gs + V t - V t

5  Devices that are normally cut-off with zero gate bias are classified as "enhancementmode"devices.  Devices that conduct with zero gate bias are called "depletion-mode"devices.  Enhancement-mode devices are more popular in practical use.

6 nMOS Enhancement Transistor  At Vds=+V, Vgs=0V, no current flows from source to drain because they are insulated by two reverse biased pn junction 1. Accumulation mode (Vgs << Vt) 2. Depletion mode (Vgs ≈ Vt) 3. Inversion mode (Vgs > Vt)

7  The factors that influence the level of drain current Ids (b/w S and D)  Distance b/w S and D  Channel width  Threshold voltage Vt  Thickness of SiO2  Dielectric constant of insulator  Carrier mobility

8  The voltage at which an MOS device begins to conduct ("turn on"). The threshold voltage is a function of (1) Gate conductor material (2) Gate insulator material (3) Gate insulator thickness (4) Impurity at the silicon-insulator interface (5) Voltage between the source and the substrate Vsb (6) Temperature

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10 V t,can be expressed as Where V t-mos is the ideal threshold voltage of an ideal transistor and V fb is termed as flat-band voltage.

11 Effect due to series connection of transistors Increases if source voltage increases because source is connected to the channel Increase in Vt with Vs is called the body effect

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14 The cutoff region is also referred to as the subthreshold region. The value of Ids is very small

15 Mobility decreases with increasing doping concentration and increasing temperature. Average carrier drift velocity (V) Electric field (E) µ=

16 Thinox Substrate SiO2 Poly Si nn Source Gate Drain  When the gate oxide is very thin, a current can flow from gate to source or drain by electron tunneling through the gate oxide. Electron Tunneling

17 The drain is at a high enough voltage with respect to the source. Causes current to flow irrespective of the gate voltage.

18 Thinox Substrate SiO2 Poly Si nn Source Gate Drain Hot elections Due to excess V ds, hot electrons impact the drain, dislodging holes that are then swept toward the negatively charged substrate and appear as a substrate current. This effect is known as impact ionization

19 Thinox p Substrate SiO2 Poly Si n n n n Source Gate Drain C gb C gd C gs C db

20 Output conductance (g ds ) in the linear region can be obtained by differentiating linear equation. The transconductance expresses the relationship between output current ids and input voltage V gs

21 1 V in V out 0 V DD GND

22 V gsn4 V gsn3 V gsn2 V gsn1 -V gsp4 -V gsp2 -V gsp1 -V gsp3 I dsn I dsp

23 Superimposing the two characteristics

24 A D C E V out V DD V in

25 A. βn/βp=10 A C B B. βn/βp=1 C. βn/βp=0.1 V in V out

26  NM L = V ILmax -V OLmax  NM H = V OHmax -V LIHmin

27 A D C E V out V DD B V in V tn V DD- V tp.5V DD

28 A. βn/βp=10 A C B B. βn/βp=1 C. βn/βp=0.1 V in V out  The ratio βn/βp is decreases the transition region shifts from left to right

29  Noise Margin:Determines the allowable noise voltage on the input of a gate so that the output will not be affect.  Noise Margin is in terms of two parameters LOW noise margin NM L and HIGH noise margin NM H

30  NM L is define as the difference in magnitude between the maximum LOW output voltage of the driving gate and the maximum input LOW voltage recognized by the driven gate.  NM L = V ILmax -V OLmax   NM H is define as the difference in magnitude between the minimum HIGH output voltage of the driving gate and the minimum input HIGH voltage recognized by the receiving gate.  NM H = V OHmax -V LIHmin 

31  Apart from the CMOS inverter, there are many other forms of MOS inverter that may be used to build logic gates  Ex: resistive load inverter  If resister value increases transfer curve leads to left side.

32  Pseudo inverter that uses a p-device pull- up or load that has its gate permanently grounded.  An n-device pull-down or driver is driven with the input signal.  βn/βp affects transfer characteristic  If nMOS on then Vout=

33  An inverter design using nMOS transistor load.  But remember that the threshold is modified by the body effect because the source of the n-load transistor above Vss

34 Thinox Substrate SiO2 Poly Si n n n n Source Gate Drain


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