1. Week 8b OUTLINE Using pn-diodes to isolate transistors in an IC
The metal-oxide-field-effect transistor (MOSFET)
Structure of the MOSFET
The MOSFET as a controlled resistance
Pinch-off and current saturation in the MOSFET
Channel-length modulation
Velocity saturation in a short-channel MOSFET
Reading
Rabaey et al. Ch
Hambley Ch. 12.1

2. Why are pn Junctions Important for ICs?
The basic building block in digital ICs is the MOS transistor, whose structure contains reverse-biased diodes.
pn junctions are important for electrical isolation of transistors located next to each other at the surface of a Si wafer.
The junction capacitance of these diodes can limit the performance (operating speed) of digital circuits

3. Device Isolation using pn Junctions
p-type Si n
regions of n-type Si a b
No current flows if voltages are applied between n-type regions, because two pn junctions are “back-to-back”
n-region
p-region a b
=> n-type regions isolated in p-type substrate and vice versa

4. Dynamic Random-Access Memory (DRAM)
Figure
0.1
Example of a densely populated integrated circuit –
the DRAM
Column Drivers and
Sense Amplifiers
Column Address
Decoder/Selector
Row Address Decoder W o
rd Line
Bit Line
Dynamic Random-Access Memory (DRAM)

5. Transistor A
Transistor B n n n n
p-type Si
We can build large circuits consisting of many transistors without worrying about current flow between devices. The p-n junctions isolate the transistors because there is always at least one reverse-biased p-n junction in every potential current path.

6. Modern Field Effect Transistor (FET)
An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying “gate” electrode), to modulate the conductance of the semiconductor
Modulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrode
Metal-oxide-semiconductor
(MOS) FET:

7. MOSFET GATE DRAIN SOURCE
NMOS: N-channel Metal
Oxide Semiconductor W
W = channel width L
L = channel length
GATE
oxide insulator n
“Metal” (heavily doped poly-Si) n
p-type silicon
DRAIN
SOURCE
A GATE electrode is placed above (electrically insulated from) the silicon surface, and is used to control the resistance between the SOURCE and DRAIN regions

8. N-channel MOSFET IG IS ID
Gate IG
Drain
Source IS
oxide insulator
gate ID n n p
Without a gate-to-source voltage applied, no current can flow between the source and drain regions.
Above a certain gate-to-source voltage (threshold voltage VT), a conducting layer of mobile electrons is formed at the Si surface beneath the oxide. These electrons can carry current between the source and drain.

9. N-channel vs. P-channel MOSFETs
NMOS
PMOS
p-type Si
n+ poly-Si
n-type Si
p+ poly-Si n+ n+ p+ p+
For current to flow, VGS > VT
Enhancement mode: VT > 0
Depletion mode: VT < 0
Transistor is ON when VG=0V
For current to flow, VGS < VT
Enhancement mode: VT < 0
Depletion mode: VT > 0
Transistor is ON when VG=0V
(“n+” denotes very heavily doped n-type material; “p+” denotes very heavily doped p-type material)

10. MOSFET Circuit SymbolsG G
NMOS
p-type Si
n+ poly-Si n+ n+ S S
Body G G
PMOS
n-type Si
p+ poly-Si p+ p+ S S
Body

11. Water Model for P-channel MOSFET

12. MOSFET Terminals
The voltage applied to the GATE terminal determines whether current can flow between the SOURCE & DRAIN terminals.
For an n-channel MOSFET, the SOURCE is biased at a lower potential (often 0 V) than the DRAIN
(Electrons flow from SOURCE to DRAIN when VG > VT)
For a p-channel MOSFET, the SOURCE is biased at a higher potential (often the supply voltage VDD) than the DRAIN
(Holes flow from SOURCE to DRAIN when VG < VT )
The BODY terminal is usually connected to a fixed potential.
For an n-channel MOSFET, the BODY is connected to 0 V
For a p-channel MOSFET, the BODY is connected to VDD

13. NMOSFET IG vs. VGS Characteristic
Consider the current IG (flowing into G) versus VGS : IG G +  S D
VDS
oxide
semiconductor + 
VGS IG
The gate is insulated from the semiconductor, so there is no significant steady gate current.
always zero!
VGS

14. The MOSFET as a Controlled Resistor
The MOSFET behaves as a resistor when VDS is low:
Drain current ID increases linearly with VDS
Resistance RDS between SOURCE & DRAIN depends on VGS
RDS is lowered as VGS increases above VT
NMOSFET Example:
oxide thickness  tox ID
VGS = 2 V
VGS = 1 V > VT
VDS
Inversion charge density Qi(x) = -Cox[VGS-VT-V(x)]
where Cox  eox / tox
IDS = 0 if VGS < VT

15. Sheet Resistance Revisited
Consider a sample of n-type semiconductor: V + _ L t W I
homogeneously doped sample
where Qn is the charge per unit area

16. NMOSFET ID vs. VDS Characteristics
Next consider ID (flowing into D) versus VDS, as VGS is varied: G ID +  S D
VDS
oxide
semiconductor + 
VGS ID
Above threshold (VGS > VT):
“inversion layer” of electrons appears, so conduction between S and D is possible
VGS > VT
zero if VGS < VT
VDS
Below “threshold” (VGS < VT): no charge  no conduction

17. MOSFET as a Controlled Resistor (cont’d)
average value
of V(x)
We can make RDS low by
applying a large “gate drive” (VGS  VT)
making W large and/or L small

18. Charge in an N-Channel MOSFET
VGS < VT:
depletion region
(no inversion layer
at surface)
VGS > VT :
VDS  0
VDS > 0
(small)
Average electron velocity v is proportional to lateral electric field E

19. What Happens at Larger VDS?
VGS > VT :
VDS = VGS–VT
Inversion-layer
is “pinched-off”
at the drain end
VDS > VGS–VT
As VDS increases above VGS–VT  VDSAT,
the length of the “pinch-off” region DL increases:
“extra” voltage (VDS – VDsat) is dropped across the distance DL
the voltage dropped across the inversion-layer “resistor” remains VDsat
the drain current ID saturates
Note: Electrons are swept into the drain by the E-field when they enter the pinch-off region.

20. Summary of ID vs. VDS
As VDS increases, the inversion-layer charge density at the drain end of the channel is reduced; therefore, ID does not increase linearly with VDS.
When VDS reaches VGS  VT, the channel is “pinched off” at the drain end, and ID saturates (i.e. it does not increase with further increases in VDS). + –
pinch-off region

21. ID vs. VDS Characteristics
The MOSFET ID-VDS curve consists of two regions:
1) Resistive or “Triode” Region: 0 < VDS < VGS  VT
2) Saturation Region:
VDS > VGS  VT
process transconductance parameter
“CUTOFF” region: VG < VT

22. Channel-Length Modulation
If L is small, the effect of DL to reduce the inversion-layer “resistor” length is significant
ID increases noticeably with DL (i.e. with VDS) ID
ID = ID(1 + lVDS)
l is the slope
ID is the intercept
VDS

23. Velocity Saturation
At high electric fields, the average velocity of carriers is NOT proportional to the field; it saturates at ~107 cm/sec for both electrons and holes:

24. Current Saturation in Modern MOSFETs
In digital ICs, we typically use transistors with the shortest possible gate-length for high-speed operation.
In a very short-channel MOSFET, ID saturates because the carrier velocity is limited to ~107 cm/sec
v is not proportional to E,
due to velocity saturation

25. Consequences of Velocity Saturation
1. ID is lower than that predicted by the mobility model
2. ID increases linearly with VGS  VT rather than quadratically in the saturation region

26. P-Channel MOSFET ID vs. VDS
As compared to an n-channel MOSFET, the signs of all the voltages and the currents are reversed:
Note that the effects
of velocity saturation
are less pronounced
than for an NMOSFET.
Why is this the case?
Short-channel PMOSFET I-V