1. Synthesis Methodology at Tundra Seniconductors
Alexander Gnusin

2. Overview Introduction Overall Methodology description
Synthesis methodology
Top Level Creation methodology
Custom IO insertion methodology
Synopsys GUI Interface enhancement

3. Introduction Motivation of this work:
Integrate EDA tools into design process
Create configurable and reusable scripting environment
Enhance Synopsys GUI Interface
Show, how TCL/TK language can be used efficiently within Synopsys environment.
Different tasks for different people:
Block-level designers prefer “push-button” approach
Synthesis / STA specialists require reusable library of configurable tcl scripts

4. Overall Methodology Description
Standard chip building blocks:
Functional Cores with ideal clock trees
Functional Logic Wrapper
Chip module contains:
Clock & Reset Generation block (PLL, gating, DFT etc)
JTAG and other test circuitry
IO buffers
Functional Logic Wrapper
Clock, Reset creation block
Functional
Cores
DFT
IO pads

5. Initial Synthesis methodology
Flatten-before-compile concept:
Removes boundaries constraints for DC
Better, than hierarchical compilation + cross-boundaries optimization (follows to the same result: inability to replace leaf blocks)
Better for STA and for Formal verification
Last Synopsys versions can compile relatively large blocks in reasonable time
Initial Synthesis Strategy:
For each core, create timing assertions file in dedicated “constr_tcl” directory.
Using read_verilog command, load all subblocks of the current Functional Core into Synopsys memory.
Uniquify and Flatten all Functional blocks, removing all subblock hierarchy.
Set synthesis constraints for the Functional block (from “constr_tcl” directory)
Run Synthesis: compile –scan
Save design: write –output <design.db> (Saved design might still have hierarchical DesignWare modules)

6. Initial Synthesis: Script Examples
Directory structure:
/run_tcl run scripts
/constr_tcl - timing assertions
/init_db - initial synthesis results
/reports – initial synthesis reports #
# Runs Initial Synthesis
proc run_syn {design vfiles} {
load_vfiles $vfiles
current_design $design
if {[link]} {
uniquify
ungroup -all -flatten
remove_design [remove_from_collection [get_designs] [current_design]]
source constr_tcl/common.tcl
source constr_tcl/$design.tcl
compile -scan > reports/$design.log
write -hier -o init_db/$design.db
remove_design -designs
} else {
echo "Error linking design $design" } #
# Reads verilog files looking on "vfiles"
proc load_vfiles {vfiles} {
set vdir [file dirname $vfiles]
set VF [open $vfiles r]
while {[gets $VF line] >= 0} {
if {[regexp {^[ ]*([^ ]+)} $line m vfile]} {
read_verilog $vdir/$vfile }
close $VF

7. Initial Synthesis: Timing Assertions
Two assertion types: common and core-specific:
common.tcl : assertions, shared between cores
<core_name>.tcl : core-specific assertions
“set_<input|output>_delay” assertions for cores:
For “external” ports, add/subtract IO buffer delay from chip-level delay info
For “internal” ports, delay can be set to <clk_period>/2 or to some other values
Discard input-to-output timing paths
Common assertion types:
set_driving_cell
set_port_fanout_number
set_fanout_load
set_load
set_operating_conditions
set_max_transition
set_max_fanout
set_wire_load_model
set_wire_load_mode
Core-specific assertion types:
create_clock
set_input_delay
set_output_delay
set_false_path

8. Cores Integration and Incremental Synthesis
First, concentrate on core’s reg-to-reg timing closure:
run “compile –map_effort high –incremental”
Increase core frequency and recompile core from RTL
Rewrite RTL code
Second, solve timing problems on Functional Logic Level:
Use timing characterization, path grouping techniques and incremental recompilation to solve timing problems
For each one of cores, discard all reg-to-reg timing paths
Third, run STA on Chip Level with Clock, Reset generation and DFT logic

9. Top-level Creation Methodology
Reduce amount of manual work for Top-level creation and buffer instantiation.
Naming convention required for the Functional Logic ports:
Signals, connected to Chip’s Input ports: <sig_name>_in
Signals, connected to Chip’s Output ports: <sig_name>_out
Signals, connected to Chip’s Input ports: <sig_name>_en
All other signals must not have these suffixes
Script “create_top” takes as input Functional Logic Wrapper, defines chip-level ports and their types and writes top-level verilog file
A_OUT
A_IN A_EN
B_IN
C_OUT
C_EN A tb B C tb

10. Top-level creation example
module example_core (
CLK,
A_IN,
A_OUT,
A_EN,
B_IN,
C_OUT,
C_EN,
// Scan ports
SI, SO );
input CLK;
input [7:0] A_IN;
output [7:0] A_OUT;
output A_EN;
input B_IN;
output [15:0] C_OUT;
output C_EN;
input SI;
output SO;
endmodule
module example_top ( B, C,
A );
// Inputs
input B;
// Outputs
output [15:0] C;
// Inouts
inout [7:0] A;
// Wires
wire [7:0] out_A;
wire [15:0] out_C;
wire en_A;
wire en_C;
//Core Module Instantiation
example_core example_core (
// Functional inputs - to pads
.A_IN (A),
.B_IN (B),
// Functional outs and enables
.A_OUT (out_A),
.A_EN (en_A),
.C_OUT (out_C),
.C_EN (en_C),
// Other signals - need to connect
.CLK (CLK),
.SI (SI),
.SO (SO) );
//Tristate buffers instantiation
tb0 #(16) pad_C (out_C, en_C, C);
tb0 #(8) pad_A (out_A,en_A, A);
endmodule

11. IO buffer parametric modeling
4 parametric modules of IO buffers:
tb0, tb1 : separate enable for each bit tb0 for active-low enable,
ts0, ts1 : common enable signal tb1 for active-high enable
// Tristate buffer, where each bit of OE controls
// corresponding path between IN and OUT
// OE is active low
module tb0 (IN, OE, OUT);
parameter bw = 1;
integer i;
input [bw - 1:0] IN;
input [bw - 1:0] OE;
output [bw - 1:0] OUT;
reg [bw - 1:0] OUT;
or IN)
begin
for(i=0; i< bw; i=i+1)
OUT[i] = OE[i]?1'bz:IN[i];
end
endmodule
//Tristate buffer, where single-bit OE controls
// all bits between IN and OUT
// OE is active low
module ts0 (IN, OE, OUT);
parameter bw = 1;
integer i;
input [bw - 1:0] IN;
input OE;
output [bw - 1:0] OUT;
reg [bw - 1:0] OUT;
or IN)
begin
for(i=0; i< bw; i=i+1)
OUT[i] = OE?1'bz:IN[i];
end
endmodule

12. Buffer insertion methodology
Use created top-level module for the chip-level functional verification.
Run real buffer instantiation only during top-level synthesis:
For regular buffers, use DC “insert_buffer” command set
For custom buffers, set of similar tcl procedures were developed
Custom buffer schematics: EN PU TN
PAD
pad PD A Y
INH YH CO CI
IDD

13. TCL procedures for custom buffers insertion
set_pinorder {pinorder_file} – reads pinorder file and sets pin order attributes for future interconnection in XOR chain
set_fpad_type {type ports} – sets buffer’s type attribute on specified ports
set_fpad_drive {drive ports} – sets buffers default drive value (pu, pd or none) attribute on specified ports
insert_fpads {} – isserts real buffers instead of parametric instances using attribute values defined by the previous commands
connect_xor_chain {} – connects buffers with sequential XOR chain using connections order, specified with “set_pinorder” command.
Running Formal verification in order to prove functional equivalency

14. Main script for buffers insertion
source tcl/focam_funcs.tcl
set_fpad_cell focam_25micron/BLVTTL [get_ports *]
set_fpad_cell focam_25micron/BPCIXT [get_ports P_*]
set_fpad_drive pu [get_ports {TDI TMS TCK TRST_}]
set_pinorder /users/agnusin/syn/pinlist.txt
insert_fpads
connect_xor_chain
set verilogout_no_tri true
write -f verilog -o results/pacman.v

15. Simple, but useful TCL procedures
proc c2l {collection} {
set my_list {}
foreach_in_collection coll_el $collection {
set el [get_object_name $coll_el]
lappend my_list $el }
return $my_list
proc rename_net {name new_name} {
set all_conn [all_connected $name]
remove_net $name
create_net $new_name
connect_net $new_name $all_conn }
proc change_plevel {cell new_ref} {
set pins [c2l [get_pins $cell/*]]
foreach pin $pins {
set net($pin) [c2l [all_connected $pin]]
disconnect_net $net($pin) [get_pins $pin] }
remove_cell $cell
create_cell $cell $new_ref
connect_net $net($pin) [get_pins $pin]
global editor
proc edit {args} {
eval $args > tmpfile
exec $editor tmpfile &
after 500 file delete tmpfile }
# 1. Set your favorite editor name:
# set editor emacs
# 2. Add “view” before command name:
# edit report_timing –max_paths 20

16. Synopsys GUI enhancement
TCL bi-directional pipeline technique allows us to launch GUI applications directly from dc_shell-t command line.
Use “syn_serv” procedure to launch TC/TK application and set up bi-directional communication between it and dc_shell-t (see example)
proc syn_serv {LoadFile} {
set TkWin [open "|$LoadFile" r+];
fconfigure $TkWin -buffering line
while {[gets $TkWin Line] >= 0} {
catch [list puts $TkWin [eval [string trim [split $Line :] "{}"]]] RetV }
close $TkWin;
proc allins {{pattern *}} {return [c2l [get_ports \*$pattern\* -filter == in"]]}
proc allouts {{pattern *}} {return [c2l [get_ports \*$pattern\* -filter == out"]]}
proc allgates {{pattern *}} {return [c2l [get_cells \*$pattern\*]]}
proc allnets {{pattern *}} {return [c2l [get_nets \*$pattern\*]]}
# Launch TK application
syn_serv search.tk
search.tcl

17. Example GUI application (client part)
proc communication {} {
global retval command
if {[gets stdin RetVal] < 0} {
return; }
set retval($command) $RetVal
proc get_data {args} {
set command [join $args :]
puts [list $command]
tkwait variable retval($command)
return $retval($command)
proc run_search {pattern type_sel} {
switch -exact -- $type_sel {
0 {return [lsort [get_data allgates $pattern]]}
1 {return [lsort [get_data allins $pattern]]}
2 {return [lsort [get_data allouts $pattern]]}
3 {return [lsort [get_data allnets $pattern]]}
fileevent stdin readable "communication";
search_window
Sets retval($command) to stdin value
Returns value from given command
Returns data list to application

18. Interactive Timing reports viewer
Some GUI Apps Examples
Reports Viewer
(Example: view report_timing –cap)
Interactive Timing reports viewer

19. Synview: more complex application
Visualizes modules hierarchy within Synopsys (clicking on the modules tree node makes corresponding design "current")
Facilitates command entry and reports viewing
Visualizes netlist connectivity within region of interest
Run “synview” directly from dc_shell-t !

20. SYNVIEW: Hierarchical Viewer

21. SYNVIEW: Netlist Viewer

22. PMAN: Running DC in background

23. Summary http://www.tclforeda.net
Simple and effective “core-based” synthesis approach
Automatic creation of manageable chip-level module
TCL/TK GUI Enhancement of all tcl-based Synopsys tools!
To get additional information & download scripts: