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Xilinx/Exemplar Logic FPGA Synthesis Solution. LeonardoSpectrum Powerful Integrated Modular ASIC & FPGA.

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Presentation on theme: "Xilinx/Exemplar Logic FPGA Synthesis Solution. LeonardoSpectrum Powerful Integrated Modular ASIC & FPGA."— Presentation transcript:

1 Xilinx/Exemplar Logic FPGA Synthesis Solution

2 LeonardoSpectrum Powerful Integrated Modular ASIC & FPGA

3 Leonardo Spectrum Bundles LeonardoInsight Giving you a choice!

4 Leonardo Spectrum User Interface  FlowTabs  provide a step by step process When the run button isn’t enough! PowerTabs  offer easy access to advanced functionality Leonardo Spectrum GUI

5 Xilinx Alliance Series LeonardoSpectrum Automatically: Transfers Constraints Creates P & R Script File Runs P & R Xilinx Place and Route Integration

6 Part of FPGA Advantage Includes all EDA Design Tools Pushbutton Simulation, Synthesis and Place and Route Provides Design Management Cross probes to everything One source for customer support

7 Virtex Optimization

8 Pipeline Multipliers  New in G (now on ftp site)  Supported for Virtex wait until clk'event and clk = '1'; temp1 <= a * b; c <= temp1; MultiplierAreaDelay Non-Pipelined Pipelined area in slices area and delay after place and route

9 Block RAM Inference (RAMB4_S1)  synchronous RAM is inferred as Block  ROMs are not inferred into Block RAM  Both single and Dual port RAMs are supported  Block RAMs include Timing arcs  Can be instantiated  Can infer distributed RAM blocks  1 Mega-bit Block RAM inferred in 20 seconds

10 Verilog Coding Example module new_ram (clk, we, din, addr, dout); input clk, we; input [7:0] din; input [4:0] addr; output [7:0] dout; reg [4:0] addri; reg [7:0] data[0:31]; clk) begin if (we == 1’b1) data[addr] = din; addri = addr; end assign dout = data[addri]; endmodule Coding Style requires both registered address and data signals New in v1999.1F

11 Controlling Block RAM Inference  Disable RAM Inference Globally > set extract_ram FALSE  Prevent RAM inference on a single instance > Set_attribute i5 –name block_ram –value false Will not be implemented in slice RAM  RTL Verilog Comment Example Reg [7:0] mem[63:0] //Exemplar attribute mem block_ram FALSE Attribute must be set on the memory storage signal

12 Slice RAM Inference  Asynchronous RAMs use the CLB RAM element Subtracts from Logic resources Library cells include timing arcs

13 DLL Cell  Inserted through instantiation  CLK_DIVIDE and DUTY_CYCLE_CORRECTION attributes are propagated to Alliance Series as EDIF properties  DLL cell does not contain timing arcs Clock constraints must be set on internal nets Set_attribute clk_internal –name clock_cycle –value 20 –net

14 BUFGDLL & BUFGDLLH Cells  Special configurations of DLL  Included in the library as a special type of clock buffer Use PAD command PAD clk BUFGDLL (Appears on wrong pull-down list)

15 SRL Inference  New in f release Turned on by Default  LUT can be used in place of registers to balance pipeline stages  Area Efficient Optimization  Controlled by 2 variables Set virtex_map_srl TRUE –enables mapping Set virtex_map_srl_pack TRUE –Packs SRL into single slice

16 SRL Example Area (slices) Delay (Mhz) previous flow srl flow % improvement 85% 16% Area (slices) Delay (Mhz) previous flow srl flow % improvement 85% 16% begin process (clk) begin if clk'event and clk = '1' then int_sig <= input & int_sig(0 to cycle - 2); end if; end process; output <= int_sig(cycle -1); end behav;

17 Priority Encoders using MUXCY  Used for implementing fast priority encoders up to 10 levels  Available through a variable called map_muxcy (default:true) To disable issue the following command from the tcl window > Set map_muxcy false  Also used for wide address decoders, wide AND gates with bubbled inputs.  Use for Alliance Series 2.1 and later

18 IOB Support Global IOB Register Inference Set virtex_map_iob_registers variable to TRUE Can be done through GUI on Technology form Tristate Enable Register : Replicates registers for the Tristate pins of IO Bus for fast Tcko. Replicates internal registers driving multiple output ports. Port by Port IOB Register Implementation Set the attribute “IOB” = true on a specific port > set_attribute out_a –name IOB –value TRUE -port

19 Virtex Optimization - F5MUX & F6MUX module mux81 (a, sel, o); input [0:7] a; input [0:2] sel; output o; assign o = a[sel]; endmodule Advanced Opt Settings  F5 MUX Any function of 5 inputs or some decomposable functions of upto 9 inputs.  F6 MUX Any function of 6 inputs or some decomposable functions of upto 17 inputs Implements upto 8x1 Mux in one CLB.

20 MULTAND  Any multiplier with non-constant operands uses the MULTAND module mult8x8 (a,b,prod); input [0:7] a; input [0:7] b; output [0:15] prod; assign prod = a * b; endmodule

21 Registers  Now inferring negative edge registers “_1” versions of cells, FD_1  Inferring synchronous set/reset flops  Inferring asynchronous set/reset flops > Set include_gates FDRS

22 Counters  All flavors of counters are implemented using 1 LUT per Bit. Loadable Synchronous Set/Reset Up/Down Count enable and clock enables  Exception include Counter with “both” asynchronous and synchronous reset and load signals.

23 Design Analysis with LeonardoInsight 2000 In Beta, Release March 2000

24 New Schematic Viewer Integrated Design Browser 10X Run time improvement Interactive to database

25 Hierarchy Schematics Shows Entire Hierarchical Schematic at once Default SchematicHierarchy Schematic

26 Critical Path Highlighting Both Filtered and Unfiltered views Constraints and Timing info displayed on Schematic

27 Fan-in, Fan-out Fragment Views Generate concise fragments of important circuits

28 Graphical Database Search

29 Interactive to Database  View connected to active database  Issue interactive commands such as group or don’t_touch  View automatically updated  View connected to active database  Issue interactive commands such as group or don’t_touch  View automatically updated

30 Managing Hierarchy

31 Creating Design Hierarchy  Use the Group Command  Will create new level of hierarchy  Original hierarchy will exist at lower level  Use to group area critical or timing critical blocks together  Can also group from the design browser CBA CB A New Group {b c} –inst new

32 Removing Design Hierarchy  Use the “ungroup” command  Will dissolve all hierarchy  Can be done from the design browser CB A New ungroup {b c} A New

33 Hierarchy Manipulation from Schematics  Hierarchy commands can be executed from schematic viewer  Schematic will automatically update

34 Moving Within Hierarchy  Present_design command can “Swap” any module into the Optimizer  Can be used for re-optimization  Can be used to Separate Blocks  All hierarchy blocks can be set to “present_design  Issue command from Design Browser or Schematic Viewer > Present_design priority_encoder B C Top A Optimization Engine

35 Module Optimization  Cannot be done through Quicksetup  Disable IO Insertion during optimization  Hierarchy may be flattened  Save netlist as “XDB” Exemplar Binary Database No netlist processing is performed Optimize Form Output Form

36 Virtex Applications

37 PCI Core Flow  Best PCI Core flow in the industry  No code modifications  Extensive hierarchy & IO buffer control  Can be 100% scripted for single pass optimization  Best PCI Core flow in the industry  No code modifications  Extensive hierarchy & IO buffer control  Can be 100% scripted for single pass optimization New Appnote available at

38 Team Design  Blocks optimized separately  Assembly done by Synthesis tool  IO Insertion, Design Analysis and Final Optimization done during synthesis New Appnote available at

39 Incremental Place and Route  Preserved Hierarchy for Incremental Place and Route  LeonardoSpectrum supports Re-opt at block level  Use Guide Files to preserve place and route timing New Appnote available at

40 Summary  Working with HDL Division to advance Methodology and ease of use  Focused on Optimization Technology  System architect for block based design  Leonardo Spectrum is the Power Tool for Virtex


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