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Copyright © 2009,Intel Corporation. All rights reserved. Auto ECO Flow Development For Functional ECO Using Efficient Error Rectification Method Based On FV Tool Andal Jayalakshmi Intel Corporation, Penang, Malaysia
Copyright © 2009, Intel Corporation. All rights reserved. Disclaimers The flow results discussed have been simulated and are provided for informational purposes only. Results were derived using EDA software tool that run on an Intels VLSI design. Any difference in VLSI design or software tool or configuration or flow may affect actual results. This work/manuscript does not in any way constitute an Intel endorsement of a product or supplier.
Copyright © 2009, Intel Corporation. All rights reserved. ECO (Engineering Change Order) ECO is a capability to integrate late RTL changes into converged netlist as re-synthesis involves high re-convergence cost Simple ECO changes may even require a lot of efforts to make the corresponding changes in the converged netlist due to the deep optimizations done by the synthesis tools. RTL Logic Synthesis Netlist Converged Netlist Scan, Clock Stitch New RTL ECO Tool Converged Netlist
Copyright © 2009, Intel Corporation. All rights reserved. Auto ECO Flow The Auto ECO Flow encompasses 5 stages which includes verification of ECO collaterals, rectification of error and verification of ECO changes made by the tool. Screen stage – Verify the netlists for old RTL and converged design for functional equivalence as a sanity check for pre-ECO collaterals. FV stage – Verify the synthesis netlists for Old and New RTL for functional equivalence to identify the failing fubs to fix. Rectification stage - Rectify the errors in each of the failing fubs iteratively and obtain the patches. Syn stage - Implement the patches on to the converged netlist to get the converged netlist with the ECO fix. Verify stage – Verify the netlists for new RTL and the converged design for functional equivalence to verify the ECO fix.
Copyright © 2009, Intel Corporation. All rights reserved. Syn netlist (for old RTL) Syn netlist (for New RTL) Converged netlist (for old RTL) FV (FV stage) Failing Fubs List Generate Fix (Rectification stage) Implement Changes (Syn stage) Converged netlist (for new RTL) FV (Verify stage) FV Status and Fix statistics ECO Change list FV (Screen stage) Sanity check FV rpt Auto ECO Flow
Copyright © 2009, Intel Corporation. All rights reserved. Sanity Check FV This is to verify if the pre-ECO synthesis netlist and the converged design (pre-ECO post-layout netlist) pass FV. This is to ensure the correctness of the pre-ECO collaterals such as the netlists and FV collaterals (scan and CTS mapping information). The FV is done at the top level as we are only interested to see if they pass or not. Pre Eco Syn Vs Pre Eco Lay (Top level) Syn netlist (for old RTL) Converged netlist (for old RTL) CTS mapping Scan ports Scan constraints FV RPT Equivalence Status
Copyright © 2009, Intel Corporation. All rights reserved. FV Collaterals – CTS Mapping The clock tree which represents more than one clock signal are to be equated to obtain functional equivalence. For example the CLK and CLK1 represent the same clock signal. Example CTS mapping # Module Dir Old New Module1 in CLK CLK1 CLK Module1 U1 DFF U2 DFF Golden Revised CLK Module1 U1 DFF U2 DFF CLK1
Copyright © 2009, Intel Corporation. All rights reserved. FV Collaterals – Scan Ports The scan ports need to be identified to constrain these to proper values to suppress the scan path from checking. Whenever the synthesis netlist is checked against converged design the CTS mapping is essential to remove the Clock and Scan signal differences. #Module scanin scanin_port Top scanin scan_in submod1 scanin scan_in #Module scanout scanout_port Top scanout scan_out submod1 scanout scan_out #Module constin constin_port value netlist Top constin scan_en 0 tar submod1 constin scan_en 0 tar Module submod1 DFF Module Top in1 in2 scan_in scan_en scan_out
Copyright © 2009, Intel Corporation. All rights reserved. FV Pre-ECO Vs Post-ECO Netlist The failing modules are identified by verifying the synthesis netlists for old and new RTL. This helps to identify the exact ECO changes to fix, which does not include the clock and scan differences. Pre Eco Syn netlist Vs Post Eco Syn netlist Hierarchical FV Syn netlist (for old RTL) Fv RPT Equivalence status for each sub module Syn netlist (for new RTL)
Copyright © 2009, Intel Corporation. All rights reserved. Error Rectification Identifies the logic in golden which are equivalent to revised using the FV tool and reuses this logic. Rectifies the error in golden by just fixing that particular portion of logic which is erroneous. Identifies and reuses the equivalent logic beyond the error boundary. Uses a BDD for functional equivalence checking during error correction. GOLDEN CONE REVISED CONE FINAL CONE Error Boundary Reused Rectified
Copyright © 2009, Intel Corporation. All rights reserved. Generating Equivalent Points Using FV tool Auto ECO Flow uses the FV tool to recursively find equivalent points. It recurses from the cone tip towards the Primary Inputs (PIs) until an equivalent point is found. The run time for this depends on the location of the error. If the error lies near to the interfaces, it will take longer run time. Interfaces
Copyright © 2009, Intel Corporation. All rights reserved. Functional Equivalence Checking Using BDDs The error rectification algorithm employs BDDs for logic function verification. These are very useful for on the fly verification compared to FV tools as they take longer time for loading the design and libraries and are more suitable for batch mode operations. The disadvantage of BDDs is that the run time and memory requirements will grow exponentially as the number of variables in the logic function increases.
Copyright © 2009, Intel Corporation. All rights reserved. Example ECO Scenario And Error Rectification Finds equivalent points as highlighted in yellow below.
Copyright © 2009, Intel Corporation. All rights reserved. Example ECO Scenario And Error Rectification contd… It marks all the cells in the sub-cone behind the equivalent points as reused ( shown in yellow) and recreates the remaining logic (shown in red) based on the ECO netlist while trying to reuse cells (shown in green) in pre-ECO netlist.
Copyright © 2009, Intel Corporation. All rights reserved. Example ECO Scenario And Error Rectification contd… Then it removes the dangling cells which have no loads recursively.
Copyright © 2009, Intel Corporation. All rights reserved. Example ECO Scenario and Error Rectification contd… This would then be the final netlist which is equivalent to the post-ECO netlist.
Copyright © 2009, Intel Corporation. All rights reserved. Converged netlist (for old RTL) Syn netlist (for new RTL) Rectification Logic ECO changelist CTS mapping Scan ports Scan constraints FUB FV rpt FUB Generate ECO Fix The rectification logic takes the netlists and FV collaterals as the inputs and generates the ECO changes as a TCL script.
Copyright © 2009, Intel Corporation. All rights reserved. Implement Changes The ECO changes are implemented using a synthesis tool. It takes in the converged netlist and the TCL script as input and generates the final netlist. The final netlist is not used directly as it is preferred to implement the changes in the same synthesis environment. ECO stitch Converged netlist (for old RTL) ECO changelist Converged netlist (for new RTL)
Copyright © 2009, Intel Corporation. All rights reserved. Post Eco Syn netlist Vs Post Eco Lay netlist Syn netlist (for new RTL) Converged netlist (for new RTL) CTS mapping Scan ports Scan constraints FV RPTEquivalence Status ECO Fix Verification The final netlist is verified for functional equivalence with the post-ECO- syn netlist. This enables the ECO change list generated by the flow to be used directly in the ECO environment for implementing the changes.
Copyright © 2009, Intel Corporation. All rights reserved. Results The flow is successfully used in Intel for various projects and the results obtained in few of the ECO executions are tabulated here. The flow is robust enough to handle complex ECOs and the user feedbacks are very encouraging. The ECO changes are found to be comparable with manual ECO changes. Though the TPT is high it was acceptable compared to manual ECOs.
Copyright © 2009, Intel Corporation. All rights reserved. Future Enhancements The TPT of the flow is high due to its functional equivalence checking mechanism. It relies upon the FV tool for finding equivalent points and BDDs for logic function verification during error correction. The future developments will be focused on improving the TPT further to exploit the fullest benefits of an automation tool to handle time critical ECOs.
Copyright © 2009, Intel Corporation. All rights reserved. Summary FV tool and BDDs were employed for the automation of the ECO flow. The ECO changes generated by the Flow was comparable to manual ECOs as per the feedback from the customers. It has improved the productivity to a large extent by reducing the ECO efforts from weeks to hours. The automation has enabled very complex ECOs which are otherwise dropped as manually fixing them is impossible due to the critical ECO schedules.
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