1. Z. Stamenković 1, M. Giles 2, and F. Russi 2 1 IHP GmbH, Frankfurt (Oder), GERMANY 2 Synopsys Inc., Mountain View, CA, USA 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Scan-Through-TAP: Combining Scan Chain and Boundary Scan Features in SOC

2. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Introduction What is Scan-through-TAP? Use of IEEE Standard 1149.1 user instruction to concatenate the internal scan chain with the BSR chain to perform a single chain operation What do we achieve implementing Scan-through-TAP? Reduction of the scan pins number Accessibility of the internal scan chains through the TAP controller Single shift path through for burn-in and diagnostics What kind of EDA tools do we need? Standard synthesis, DFT, BSD, and ATPG tools

3. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 DFT/BSD in SOC Design Flow yes Applications System Specification System Specification Library Database New Modules Customisable Modules (synthesisable RTL code) Configurable Modules (synthesisableRTL code) Predefined Modules (synthesised net-list, SDF and/or LEF) Predefined Modules (memory and custom blocks) Simulation OK? HDL Model Definition HDL Top Module Definition Logic Synthesis Simulation OK? Layout Synthesis no yes no Simulation OK? Final Chip Layout yes no Test Benches Layout Re-synthesis Sufficient? yes Logic Re-synthesis Sufficient? yes no New Modules ATPG DFT/BSD

4. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Scan Insertion Flow Read in synthesized design Define clock constraints Define scan chain Insert scan chains Write out scan test protocol and netlist for TetraMAX Read Design Create Test Protocol Specify Scan Architecture Insert Scan Paths Handoff Design DFT DRC Preview DFT DRC Coverage

5. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Boundary Scan Insertion Flow Set BSD STT specifications Preview BSD Insert BSD logic (Synthesis integrated) Insert BSD logic (Synthesis integrated) BSD Gate Level Netlist BSD Gate Level Netlist Read Pin Map Check IEEE 1149.1 Std compliance Check IEEE 1149.1 Std compliance BSDL File BSD Patterns BSDL File BSD Patterns 1149.1 BSD Inserted design Lib Read design netlist Lib Preview your JTAG design Insert your JTAG logic Write out final netlist Write BSDL file and patterns (optional) Check compliance to IEEE 1149.1 STD Write BSDL file and BSD patterns Write the STIL protocol file for ATPG Read technology synthesis libraries Read scanned ready netlist with IOs Set TAP FSM specification Set STT specification Read pin map for die package BSR order

6. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Scan-Through-TAP Register

7. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Netlist & SPF TetraMAX ATPG TetraMAX ® ATPG ATPG Patterns RTL Design Compiler BSD Compiler JTAG Insertion DFT Compiler Test Synthesis Functional Patterns STT Test Patterns

8. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Implementation Results (1) SOC features 0.25 µm CMOS technology 23 mm 2 of silicon area 2.5 mm 2 occupied by memory ~ 1 million transistors 104 functional ports 12 inputs 44 outputs 48 bidirectional 5 TAP ports TRST TCK TMS TDI TDO

9. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Implementation Results (2) Single scan register made of around 15000 scan flip-flops Boundary scan register of 151 cell 5 TAP instructions BYPASS EXTEST PRELOAD SAMPLE STT 32000 BSD functional test patterns 1151 ATPG test patterns Chip area overhead below 7% Caused by insertion of scan flip-flops and boundary scan logic Combined fault coverage is slightly above 94%

10. 13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008 Summary Scan-Through-TAP methodology provides the infrastructure for both testing of systems internal nodes and testing of systems boundary circuitry A good solution for pin limited SOC designs A middle-size processor-based SOC used for implementation Results show small chip area overhead, acceptable number of test patterns, and high fault coverage