1. IC-Brazil Program created by MCT in 2005
Elimine o RETÂNGULO de TEXTO e INSIRA o logotipo da DH.
Jacobus W. Swart
CTI 1

2. Outline Vision & Activities Organization Design houses Manufacturing
Training HR
Opportunities
Tópicos da Apresentação 2

3. Vision & Objectives
To promote the development of an ecosystem in microelectronics in Brazil and the insertion of Brazil in the semiconductor market
Promote local IC companies
Attraction of international companies
E.g., Freescale – today 200 IC designers
Smart - Back-end fabrication
Promote electronics innovation
Synergy with other governmental incentives:
Informatics law
PADIS – new program for semiconductors and displays
Subvention programs by FINEP and BNDES

4. Activities Support for design houses Support for fabrication:
Wafer fabrication
Packaging and
Testing of IC´s
IC design training program 4

5. IC-Brazil Organization
Steering Committee & 3 sub-committees
Infrastructure
Education
Business
Executive Office
Located at CTI, Campinas 5

6. Design Houses
7 Design Houses Already in Operation 6

7. Design Houses Cadence's Tool Training Fellowships in the first years
Infrastructure
Workstations
Cadence's Software Tools
Cadence's Tool Training
Fellowships in the first years
Current 97 fellowships for 133 designers
IC Design
IP Library
Comercial Designs: 19 finished & 18 in progress
Next steps: growth of existing DH´s and increase number to 15 DH´s until 2010 7

8. LINCS-CETENE Team: Expertise: 25 designers 5 trainees
Modeling in System C
Design with Verilog-VHDL RTL
Functional verification using SCV
Prototyping with FPGA (Altera)
Silicon layout (Cadence)

9. 100% first time silicon success
LINCS - CETENE
PORTIFÓLIO
100% first time silicon success
e first price at IP/SoC 2006.
CAIP - Controle Automático de Iluminação Pública

10. Design House - CTI DH CTI Technologies:
Mixed analog- digital IC design
Mixed RF and RFID
Mixed Smart Power
SoCs: FPGA and Structured ASICS
Some Figures
Human Resource – 25 designers
Infrastructure:
400 m2 ( ~ 4500 sq ft) Lab area
50 workstations
Tools: Cadence, Mentor Graphics, Altera, ...
Projects & Services
Intelbras FINEP/VAEE
Intelbras FINEP/IPSVAEE
CIS Eletrônica FINEP/DECOD
ICs, Sensors, FPGAs, … DH
CTI
Foundries Relationship
IBM BiCMOS technology 0,35um and 0,18um – Analog and RF
XFAB 1um, 0,6um, 0,35um and 0,18um – Analog, RF, HV (650V), Sensor and MEMs
Austriamicrosystems CMOS & BiCMOS 0,35um – Analog, RF
NEC – Structured ASICs

11. LSITEC Analog & Mixed Mode Design Digital ASIC / FPGA
25 design engineers working in two offices:
Sao Paulo (SPO)
Salvador (SO, Bahia State)
70% with MsC or PhD
2 Engineers have more than 15 years experience in US design companies

12. Response Time to Repair has been reduced by 2/3
IC Design
Signaling device, battery operated, to identify power interruptions in high power transmission lines
Outcome
Response Time to Repair has been reduced by 2/3
Mixed Mode IC developed in 3 months, from specs to tapeout
Layout (left) and under test (right) Industrial production starts on April 2008
(using smd package)

13. Manufacturing Wafer fabrication: Packaging Testing foundries
CEITEC: 0.6 µm CMOS, start 2009
Packaging
Service providers
CTI
Testing
CTI and others 13

14. CEITEC – Wafer Fab and Design Center1 2
Building m2
Design Center
Marketing
Process engineering
Technological incubator
Training Facilities
Building m2
2.000 m2 Clean rooms of production and training (800 m2 class100)‏
4.000 wafers/month
(200 a chips/ wafers)‏

15. Packaging at CTI
Small scale ceramic packaging – engineering phase of IC design
Chip on Board (COB) technology for prototyping;
Packaging of sensors and SAW devices
Microsoldering of Al and Au wires
Special dicing for different substrates:
Si, GaAs, Al2O3, LiNbO3, glass, quartz, circuit boards, etc.

16. Characterization and Failure Analysis
Teradyne MicroFlex tester
Logic analyzer-HP16500B
Wafer prober – Micromanipulator 6400
Optical Microscope
SEM w. EDX/WDS
FIB/SEM dual beam
CCS-UNICAMP)

17. Reliability and Certification
Thermal cycling chamber Vötsch 7012
Climatic chamber – Vötsch 7033
Burn-in
Sample preparation

18. Training Program Cadence's Partnership
1 Yr. Training Program (Digital, Analog & RF)
Certification of Brazilian Instructors
Objective ~ designers in 3 to 4 years
First Training Centers in Porto Alegre and Campinas 18

19. Training Program 4 Training Centers
CT#1 – Porto Alegre, RS (Started on April 2008)
CT#2 – Campinas, SP (Started on August 2008)
CT#3 – TBD (On July 2009)
CT#4 – TBD (On January 2010)
400 students per year from 2009
Phases
4 months – Theory & Tool Training
8 months – Specific Commercial Project
Instructors & Training Content
1st year – Cadence's Team
Training Content Designed by Cadence 19

20. Additional Training
Master & PhD programs in Brazil – estimate: 100 MSc + 40 PhD / year.
One year master program in France: university & ST Microelectronics – 12 students / year
On the job training at Freescale: 24 engineers

21. Opportunities DHs have strong demand for designers
In the Training Centers
Lectures
Instructors
Lab Assistants
Team Leaders
New Network Program: SIBRATEC
Microelectronics
Electronics Products Quality
Photovoltaics 21

22. Financial Support 22

23. Centro de Tecnologia da Informação Renato Archer
Figures:
Campus area = m2
Building area = m2
People = 300