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Eri Prasetyo Wibowo Universitas Gunadarma

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1 Eri Prasetyo Wibowo Universitas Gunadarma

2 DIFINISI System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on one chip. A typical application is in the area of embedded systems. ( wikipedia)computerelectronic systemintegrated circuit digitalanalogmixed-signalradio-frequencyembedded systems System-on-a-chip (SoC) technology is the packaging of all the necessary electronic circuits and parts for a "system" (such as a cell phone or digital camera) on a single integrated circuit ( IC ), generally known as a microchip.ICmicrochip For example, a system-on-a-chip for a sound-detecting device might include an audio receiver, an analog-to-digital converter ( ADC ), a microprocessor, necessary memory, and the input/output logic control for a user - all on a single microchip.ADCmicroprocessormemoryinput/output

3 MOORE’S LAW: 2X FUNCTIONALITY EVERY 18 MONTHS Base Design CPU IC Shrinks CPU Or Keep Package Same Size CPU FPGA EEPROMRAM ADC SoC

4 DESIGN PRODUCTIVITY LAGS MANUFACTURING CAPABILITY Maya Rubeiz USAF Wright Labs

5 Application Space HW-SW Kernel MEM FPGA CPU Processor(s), RTOS(es) and SW architecture *IP can be hardware (digital or analogue) or software. IP can be hard, soft or ‘firm’ (HW), source or object (SW) *IP can be hardware (digital or analogue) or software. IP can be hard, soft or ‘firm’ (HW), source or object (SW) Scaleable bus, test, power, IO, clock, timing architectures + Reference Design Programmable SW IP Hardware IP Pre-Qualified/Verified Foundation-IP* Foundry-Specific HW Qualification Reconfigurable Hardware Region (FPGA, LPGA, …) SW architecture characterisation SOC PLATFORM DESIGN

6 FPGAs can contain soft or hard IP (including CPUs). RECONFIGURABLE FPGA-BASED BOARDS CAN PROTOTYPE DIGITAL DESIGNS

7 DESIGN-FOR-REUSE and DESIGN-WITH-REUSE APPLICATION REQUIREMENTS FPGAFPGAFPGAFPGA VERIFICATION DESIGN FOR REUSE HDLHDLHDLHDL TEAM PROJECT SoC DESIGN WITH REUSESYSTEM INTEGRATION

8 SOC WITH RECONFIGURABLE COMPONENTS High performance ASICs can now contain programmable logic (embedded FPGA tiles) as needed for flexibility. ARM

9 A matrix of configurable analog opamps and interconnect can be used to perform filtering and other signal conditioning operations. CONFIGURABLE ANALOG ARRAYS

10 RADIATION-TOLERANT CIRCUITS CAN BE MADE USING CONVENTIONAL PROCESSES SDG Conventional Transistor Layout Radiation Effects Current (Drain) Voltage (Gate) Desired Behavior SD G Radiation-Tolerant Layout REF: cern.chcern.ch

11 SHARING MULTI-PROJECT MASKS AND WAFERS SAVES MONEY Shared, Multi-Project WaferSingle-User Wafer

12 MULTI-PROJECT SERVICES PROVIDE ACCESS TO STATE-OF-THE-ART COMMERCIAL PROCESSES

13 PROCESSES AVAILABLE VIA MOSIS TSMC 0.35µTSMC 0.35µ TSMC 0.25µTSMC 0.25µ – 5-metal, 2-poly TSMC 0.18µTSMC 0.18µ –6-metal –2.5/3.3v I/O, 1.5/1./8v Core Peregrine SOI-SOS 0.50µPeregrine SOI-SOS 0.50µ TSMC 0.15µTSMC 0.15µ TSMC 0.13µTSMC 0.13µ –6-metal, 1 poly, silicided, Cu IBM SiGe 0.5µIBM SiGe 0.5µ IBM SiGe 0.25µIBM SiGe 0.25µ NOWNEXT 6 MONTHS

14 Assemble individual components using a board with reconfigurable interconnect to finalize the system specs. Model the entire system and simulate at a high level. STEPS IN MIXED-SIGNAL SOC DEVELOPMENT Design and prototype an analog I.C. via MOSIS or CMP. Design and prototype the digital components using FPGAs. Integrate the analog and digital sections into a single SoC. SoC

15 BAGAIMANA MEMULAI DESAIN DALAM SOCs


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