Presentation on theme: "Bias Voltage Generation. Use Cascode to Increase output Resistance Rout is approximately g m3 r o3 r o2 L1=L2, but L3 need not equal to L2. Design Criteria:"— Presentation transcript:
Accuracy and Voltage Headroom Trade-Off Vb is chosen to allow minimum VP. Problem: VX is not equal to VY Iout is not equal to Iref. Vb is chosen to allow VX=VY VP is not minimum. But Iout is equal to Iref.
Design Criteria Desirables: – I OUT should be I REF. (i.e. V X =V Y ) – V out should be minimized. (i.e. V OD2 +V OD3 ) V OUT =V OD3 +V OD4 V A =V B →I OUT =mI REF IREF produces VGS1 and VGS3. If VA is to be defined by Vb, then VD1 must not be connected to VG1, otherwise, it becomes unclear which node defines VA.
VOD3=0.163 V VOD4=0.056 V VOUT(min)=VOD3+VOD4=0.219 V
Vb Generation (Option 1) Requirement: Vb=V OD2 +V TH2 +V OD1 V GS5 =V GS2 V OD1 =V GS6 -I 1 R b Problem: M5 suffers from no body effect M2 suffers from body effect Rb is not well controlled, unless Rb is off-chip.
Vb Generation (Option 2) Requirement: Vb=V OD2 +V TH2 +V OD1 V GS5 =V GS2 V OD1 =V GS6 -V TH7 Problem: M5 suffers from no body effect M2 suffers from body effect Design M7 (Large W 7 /L 7 ) so that VGS7 is approx. VTH7 Need to have sufficiently large VGS6, otherwise M6=triode since M7=Sat.