Design Procedure Decide on an IC that yield to proper gm and rπ. Choose a proper I C R E, e.g. 200 mV. Determine Vx given IC and I C R E. Choose R1 and R2 to provide necessary value of VX and establish I1>>IB. Select an RC to place the transistor at the edge of saturation.
Example 1 Specification – gm=19.2 mS→IC=0.5 mA Assume that VRE=200 mV. – RE=0.2 V/IC=400 Ohms Calculate VBE – VBE=V T ln(IC/IS), IS=6.734x10 -15 A→VBE=0.65 V Calculate VX=VBE+VRE=0.65+0.2V=0.85 V
Example 1(Cont.) IC=0.5 mA, β=150→ IB=3.33 uA I1>>IB. Let’s say that I1=40IB. →I1=133.3 uA Assume that VCC=12 V. →R1+R2=VCC/I1→R1+R2=90 KOhms Vx=VBE+RE*IC=R2*VCC/(R1+R2)→R2=6.38 KOhm R1=(R1+R2)-R2=90 Kohms-6.38 Kohms=83.619 Kohms Place Q1 at the edge of Saturation: VCC- RC*IC=VX→RC=22.30 KOhms
Comparison Designed Value ADS Simulation IC0.5 mA0.463 mA VBE0.65 V0.641 V VX0.85 V0.828 V IB3.33 uA3.83 uA I1133.3 uA134 uA VRE200 mV187 mV I1/IB4034.98
Sensitivity to Component Variation Nom.1%5% R3 (KOhm) 6.386.446.69 VBE (mV)0.6410.6520.644 IB (uA)3.833.94 uA5.43 IC (mA)463 uA 477 uA521 uA 1% error in R3 leads to 3 % error in IC. 5% error in R3 leads to 12.5 % error in IC.
Increase VRE to 400 mV Nom.1%5% R3 (KOhm) 7.887.968.27 VBE (mV)0.6390.641 IB (uA)3.903.994.55 IC472 uA 483 uA519 1% error in R3 leads to 2.3 % error in IC. 5% error in R3 leads to 9.9 % error in IC.
Trade-Off As VRE increases, the circuit becomes slightly less sensitive to Resistor variation But VCE also drops, increasing the likely hood that the circuit can be driven into saturation.
Output/Input Impedance It is desirable to maximize the input impedance and minimize the output impedance of the amplifier.
Measurement of Input/Output Imepdance Open, because the output Is not connected to any external source Disable the effect of any input voltage Source. 1.Apply a test voltage (Vx) 2.Measure the resulting current (IX) 3.Calculate Vx/IX
DC and Small-Signal Analysis 2-step analysis: 1.DC analysis 2.Small signal analysis (Premise: the change in IC due to the signal must remain small)
Summary of Impedances Seen at Terminals of a Transistor (Into the base) (Into the collector)(Into the emitter)
Input Impedance Derivation of Input Impedance of Degenerated CE Stage Input Resistance with no emitter resistance Input Impedance with Base Resistance Input Impedance with Bias Resistors included
Input Impedance of the Degenerated CE Stage Interpretation: Any impedance tied between the emitter and ground is multiplied by (Beta+1) when seen from the base.
Input Resistance without Emitter Degeneration Resistor R in =r π
Input Impedance Including the Biasing Resistors (EQ 5.226)