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Common Emitter Amplifier

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Design Rules V RE should be > 100 mV.

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Design Procedure Decide on an IC that yield to proper gm and rπ. Choose a proper I C R E, e.g. 200 mV. Determine Vx given IC and I C R E. Choose R1 and R2 to provide necessary value of VX and establish I1>>IB. Select an RC to place the transistor at the edge of saturation.

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Example 1 Specification – gm=19.2 mS→IC=0.5 mA Assume that VRE=200 mV. – RE=0.2 V/IC=400 Ohms Calculate VBE – VBE=V T ln(IC/IS), IS=6.734x10 -15 A→VBE=0.65 V Calculate VX=VBE+VRE=0.65+0.2V=0.85 V

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Example 1(Cont.) IC=0.5 mA, β=150→ IB=3.33 uA I1>>IB. Let’s say that I1=40IB. →I1=133.3 uA Assume that VCC=12 V. →R1+R2=VCC/I1→R1+R2=90 KOhms Vx=VBE+RE*IC=R2*VCC/(R1+R2)→R2=6.38 KOhm R1=(R1+R2)-R2=90 Kohms-6.38 Kohms=83.619 Kohms Place Q1 at the edge of Saturation: VCC- RC*IC=VX→RC=22.30 KOhms

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Comparison Designed Value ADS Simulation IC0.5 mA0.463 mA VBE0.65 V0.641 V VX0.85 V0.828 V IB3.33 uA3.83 uA I1133.3 uA134 uA VRE200 mV187 mV I1/IB4034.98

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Sensitivity to Component Variation Nom.1%5% R3 (KOhm) 6.386.446.69 VBE (mV)0.6410.6520.644 IB (uA)3.833.94 uA5.43 IC (mA)463 uA 477 uA521 uA 1% error in R3 leads to 3 % error in IC. 5% error in R3 leads to 12.5 % error in IC.

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Increase VRE to 400 mV Nom.1%5% R3 (KOhm) 7.887.968.27 VBE (mV)0.6390.641 IB (uA)3.903.994.55 IC472 uA 483 uA519 1% error in R3 leads to 2.3 % error in IC. 5% error in R3 leads to 9.9 % error in IC.

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Trade-Off As VRE increases, the circuit becomes slightly less sensitive to Resistor variation But VCE also drops, increasing the likely hood that the circuit can be driven into saturation.

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What if we drive the base with a small signal?

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Input and Output Vout, m=46 mV Vin, m=1 mV

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Replace the transistor by its small signal equivalent circuit (EQ 5.157) Comparision: ADS Simulation: 46 EQ 5.157: 49.33

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Trade-Off of Design Sensitivity and Gain VREREAV 00436.50 0.120089.27 0.240049.33 0.360033.89 0.480025.7

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Idea: Apply degeneration to the biasing, but not to the signal! Zc at 1 KHz: 159.2 mOhms

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Av=349

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Output/Input Impedance It is desirable to maximize the input impedance and minimize the output impedance of the amplifier.

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Measurement of Input/Output Imepdance Open, because the output Is not connected to any external source Disable the effect of any input voltage Source. 1.Apply a test voltage (Vx) 2.Measure the resulting current (IX) 3.Calculate Vx/IX

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DC and Small-Signal Analysis 2-step analysis: 1.DC analysis 2.Small signal analysis (Premise: the change in IC due to the signal must remain small)

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Summary of Impedances Seen at Terminals of a Transistor (Into the base) (Into the collector)(Into the emitter)

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Input Impedance Derivation of Input Impedance of Degenerated CE Stage Input Resistance with no emitter resistance Input Impedance with Base Resistance Input Impedance with Bias Resistors included

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Input Impedance of the Degenerated CE Stage Interpretation: Any impedance tied between the emitter and ground is multiplied by (Beta+1) when seen from the base.

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Input Resistance without Emitter Degeneration Resistor R in =r π

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Input Impedance Including the Biasing Resistors (EQ 5.226)

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Input Resistance with RB in Series

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Output Impedance Derivation of Output Impedance with Emitter Degeneration Resistance Output Impedance without Emitter Degeneration Resistance

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Output Impedance Derivation

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Without Emitter Degeneration Rout=r o

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Output Impedance (If Early Effect is negligible) Rout=RC

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Gain Modification Gain of a Degenerated Common- Emitter Amplifier Without Emitter Degeneration Gain with a base resistance Gain with biasing resistors

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Emitter Degeneration

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Without Emitter Degeneration

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Gain with a base resistance

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General CE Stage

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PNP CE Amplifier

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Calculation

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Voltage Gain Analytical: 13.80 ADS Simulation: 13.4

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Example 2: Multistage Amplifier

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Multistage Amplifier Calculation

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ADSAnalytical Av15.25.78 Av217.913518.59 Av93.15107.45

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