1. Advancing Strained Silicon A O’Neill, S Olsen, University of Newcastle P-E Hellstrom, M Ostling, KTH K Lyutovich, E Kasper, University of Stuttgart

2. Scope First investigation of thin VS MOSFETs –10x reduction in virtual substrate thickness –Reduced self-heating –Reduced growth time –Compare thin with thick VS MOSFET

3. SiNANO collaboration WP1 –Stuttgart –KTH –Newcastle

4. Strained Si Material Growth IDIL growth T (°C)Processed wafers A1669550 A1670575T1 A1671600 A1672625 A1673650T2 A1674675 Si control

5. Processing Device isolation: deposited oxide Gate oxide: 2.8 nm Poly-Si: 150 nm Spacer formation: TEOS/Si 3 N 4 Source/Drain implants: As + 950 °C RTA Silicide: 20 nm NiSi Isolation: 200 nm low temperature oxide Metalisation: TiW (120 nm) and Al (500 nm)

6. nMOSFET no cross-hatching or dislocation pile-ups

7. Wafer yield T2 T1Si control 53.4%89.7%65.5%  yield not determined by material quality (yield on Si control is only 65%) L g = 10  m

8. Short-channel performance High performance strained Si MOSFETs Only small self-heating, despite high I d High knee voltage for T2 devices L g = 0.35  m V g -V t = 1,2,3 V T2 T1 Si control

9. Series resistance: silicide R sh Si < R sh T1 < R sh T2 Same trend for NiSi on gate => primarily a process issue R sh (ohm/sq) T2 T1 Si control Minimum 49 107 Maximum 99 117 Median 69 108

10. Series resistance: contacts R c Si << R c T1 << R c T2 Problems with Al-TiW-NiSi source/drain contacts for strained Si wafers R c (ohms) T2 T1 Si control Minimum 42 14 3.8 Maximum 7700 979 15.6 Median 3090 126 8.6

11. FIB investigation of contacts smooth contact, no overetch rough contact, much overetch (~160 nm) T1 T2 Overetch of vias resulting in contact to SiGe virtual substrate (caused by thin silicide layer reducing etch selectivity?)

12. Impact of R s on short channel performance L g = 0.35  m High R sh and R c degrade g m max 0 50 100 150 200 250 300 350 400 020406080100 source/drain sheet resistance R sh (ohms/sq) maximum transconductance g m max at V d = 1.0 V (mS/mm) T2 T1 Si control 0 50 100 150 200 250 300 350 400 110100100010000 contact resistance R C (ohms) maximum transconductance g m max at V d = 1.0 V (mS/mm) T2 T1 Si control

13. Impact of R s on long channel performance L g = 10  m Little impact of high R sh and R c on long channel performance => concentrate analysis on large geometry devices 0 5 10 15 20 25 30 020406080100 source/drain sheet resistance R sh (ohm/sq) maximum transconductance g m max at V d = 1.0 V (mS/mm) T2 T1 Si-control = 1.0 V (mS/mm) T2 T1 Si-control

14. Device performance: I off dependence on material V d = 0.1 V V d = 1.0 V L g = 10  m I off (T2) > I off (T1) > I off (Si) Only T2 wafer exhibits large cross-wafer variation in I off T2 T1 T2 T1 V d = 0.1 V

15. Cross-wafer variation: I off V d = 0.1 V, L g = 10  m T2 T1Si control

16. Sub-threshold summary Best performanceT2T1Si control I off (pA/  m) 21005.30.26 SS (mV/dec)1319579 DIBL (mV/V)8<<20 L g = 10  m, Vd = 0.1 V Median performanceT2T1Si control I off (pA/  m) 43006.70.33 SS (mV/dec)1659680 DIBL (mV/V)22<<20

17. Device performance: I off dependence on V d Both SSi wafers exhibit large dependence of I off on V d Electrical measurements confirm Ioff dominated by substrate current L g = 10  m T2 T1 T2

18. Origin of leakage: n+/p junction n=1.45  recombination sites x j ~120 nm  intermediate SiGe layer

19. Origin of leakage: defects Reverse processing on best-performing devices (gate regions) Schimmel etch consisting of CrO 3 /HF Increased defect density on material grown at T2 100  m Etch pit density: 2.2x10 6 cm -2 100  m T2T1 Etch pit density: 9x10 5 cm -2

20. C-V characteristics Low T High TSi control No difference in EOT between wafers (~ 3 nm) C-V measurements carried out on 50  m x 100  m MOS capacitors

21. 1.E+11 1.E+12 1.E+13 T1T2Si Control D it (cm -2 eV ) Median Best Gate oxide quality Regardless of gate length: – No impact of SiGe virtual substrate on D it – No correlation between g m max and D it ! best 10  m diebest 0.35  m die 1.E+11 1.E+12 1.E+13 T1T2Si Control D it (cm -2 eV ) Median Best

22. Surface roughness AFM measurements carried on 20  m x 20  m scan areas No clear impact of growth T on surface roughness T1 T2

23. Analysis by Raman Spectroscopy Raman spectra provide information on Ge composition, channel thickness, virtual substrate thickness and channel strain. Shift in peak for Si-Si in SiGe indicates fluctuation in VS Ge composition Spectra may also be influenced by defectivity = 514.5 nm IL growth T = 675 degC Si-Si bond in Si substrate Si-Si bond in Si channel Si-Si bond in SiGe VS

24. Ge-strain correlation As-grown channel stress follows VS Ge composition Processed channel strain measurements in progress T1T2

25. Drain current enhancements ~ Uniform enhancements in I on with V d suggest little self-heating L=W=10um T1 T2 T1 Si

26. Mobility enhancement ~ 50%

27. Device performance: g m L g = 10  m V d = 0.1 V T2 T1 Si

28. Cross-wafer variation: g m V d = 1.0 V, L g = 10  m 0 5 10 15 20 25 30 791113151719212325 T2 T1 Si Count Maximum transconductance gm (mS/mm)

29. Impact of gate length on g m max Expected increases in g m max at smaller L g observed V d = 0.1 VV d = 1.0 V T1 T2 Si T1 T2 Si

30. Impact of gate length on g m max T1 Reduced enhancements for high V d – self heating?

31. Impact of gate length on g m max T1 Olsen et al, J Appl Phys (2005) Reduced enhancements for high V d – self heating? Greater impact of self heating for thick virtual substrate

32. Impact of gate length on g m max T1 Olsen et al, IEEE Trans ED (2003) Reduced enhancements for high V d – self heating? Greater impact of self heating for thick virtual substrate Same increase in enhancement for low Vd for thick virtual substrate (x=0.15)

33. Cut-off frequency vs. gate length ~100 % enhancement in cut-off frequency for strained devices W = 5 μm V d = 1.2 V

34. Cut-off frequency vs. gate length ~100 % enhancement in cut-off frequency for strained devices gate width increases cut-off frequency de-embedded pads (not circuit model) W = 5 μm V d = 1.2 V L g = 1 μm V d = 1.2 V

35. Summary First thin virtual substrate MOSFETs Enhanced performance reduced self heating (cf thick VS) RF performance demonstrated