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**Modular Combinational Logic**

Chapter 4 Modular Combinational Logic

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Decoders

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Decoders n to 2n decoder n inputs 2n outputs For each input, one and only one output will be active. Uses: “Minterm generator” Wordline (memory) circuit Code conversion Routing data

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2 to 4 Decoder Example

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**2 to 4 Decoder – Truth Table**

X1 X0 Y3 Y2 Y1 Y0 1

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2 to 4 Decoder Equations

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2 to 4 Decoder: Circuit

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**2 to 4 Decoder: Block Symbol**

Circuit

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3 to 8 Decoder Example

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**3 to 8 Decoder – Truth Table**

x2 x1 x0 y7 y6 y5 y4 y3 y2 y1 y0 1

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3 to 8 Decoder Equations

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3 to 8 Decoder: Circuit

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**3 to 8 Decoder: Block Symbol**

Circuit

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Design Example

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Example Using only a 3x8 decoder and two-input OR gates, design a logic circuit which implements the following Boolean equation

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Solution m2 m4 m5

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2 to 4 Decoder with Enable

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**2x4 Decoder with Enable Enable is abbreviated as EN**

EN is called a Control Signal Control Signals can be Active High Signal EN = 1 – Turns “ON” Decoder Active Low Signal EN=0 – Turns “ON” Decoder

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**2 x 4 Decoder with Active High Enable – Truth Table**

y3 y2 y1 y0 1

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**2 to 4 Decoder with Enable Equations**

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**2 to 4 Decoder with Enable Circuit**

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**2 to 4 Decoder with Enable Symbol**

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**2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation)**

y3 y2 y1 y0 d 1 d = don’t care En has “highest” priority. If En=0, we “don’t care” about x1 or x0 because Y=0

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**2 x 4 Decoder with Active Low Enable – Truth Table (Short hand notation)**

EnL x1 x0 y3 y2 y1 y0 1 d d = don’t care En has “highest” priority. If En=1, we “don’t care” about x1 or x0 because Y=0

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**2 to 4 Decoder with Active Low Enable Circuit**

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Design Example

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Example Design a 3x8 decoder using only 2x4 decoders and NOT gates.

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Solution “On” when A=0 “On” when A=1

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TPS Quiz

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Encoders

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**Encoders Opposite of a decoder 2n to n encoder**

2n inputs n outputs For each input, the circuit will produce an “encoded” output

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**Example: 4 to 2 Binary Encoder Truth Table**

1 Assume only one input high at a time!!

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4 to 2 Encoder Equations

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**Problems with initial design**

Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1? A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low.

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**Problems with initial design**

If IA = 1 => all lines are 0 If IA = 0 => at least one line is 1 Q: What happens if more than one input is high at the same time? A: Design a “priority” encoder that will encode the input with the highest priority. Let’s set X3 with the highest priority, followed by X2, X1, and X0

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**Example: 4 to 2 Priority Binary Encoder Truth Table**

1 d

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Solution 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y1 Y0

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**4 to 2 Priority Encoder Equations**

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**Multiplexer/Data Selectors**

MUX Very Important Module!!!

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**Multiplexer(MUX)/Data Selector**

N to 1 multiplexer n data input lines Log2(n) control inputs One output This circuit will “connect” the selected input to the output. The selected input is specified by a decoding of the control inputs.

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**Example: 4 to 1 MUX Truth Table**

Control Inputs Output Data Inputs D3 D2 D1 D0 A B F d 1 d = don’t care / Di = data on input i

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4 to 1 MUX Equation D’s are the DATA inputs, AB are control inputs and called the “select” lines.

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**4 to 1 MUX Circuit Control Inputs Data Inputs Output 2x4 Decoder**

Only a single AND gate will be “ON” at a time.

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4 to 1 MUX Symbol Data Inputs Output Control Inputs

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**Data and Control Paths Control Path Outputs Logic Data Path Data Path**

Inputs Data Path Outputs Control Path Inputs

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MUX Applications

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**Example Using a 4x1 MUX, design a logic circuit which implements:**

We have, Y

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**Example Using a 4x1 MUX, design a logic circuit which implements: a b**

Y Dn D0 1 D1 D2 D3

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Solution

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**Multibit Multiplexers**

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**Multi-bit Multiplexers**

J-bit nx1 mux d0 d1 J bits deep d2 F J bits deep … dn-1 sel log2n j=0 to 3 This is just J separate nx1 multiplexers

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**Example 4-bit 4x1 MUX D0[3..0] D0[3..0] D1[3..0] D1[3..0] F[3..0]**

4 bits deep D2[3..0] D3[3..0] D3[3..0] A B A B j=0 to 3 This is just 4 separate 4x1 muxes

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Example 4-bit 4x1 MUX Bit 0 Bit 1 Bit 2 Bit 3

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**Example 4 bit 4x1 MUX For the jth output, we have D0[j] D1[j] D2[j]**

F[j] D3[j] A B

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**Example 4 bit 4x1 MUX For the bit 0 output, we have D0[0] D1[0] D2[0]**

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**Example 4 bit 4x1 MUX For the bit 1 output, we have D0[1] D1[1] D2[1]**

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**Example 4 bit 4x1 MUX For the bit 2 output, we have D0[2] D1[2] D2[2]**

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**Example 4 bit 4x1 MUX For the bit 3 output, we have D0[3] D1[3] D2[3]**

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**Example 4 bit 4x1 Mux Complete Circuit Bit 0 F[0] Bit 1 F[1] F[2]**

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Example 4 bit 4x1 MUX Symbol

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Design Example Using a 4bit 4x1 MUX, design a 8bit 4x1 MUX

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Solution

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**DeMultiplexers/ Data Distributors**

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**Demultiplexer/Data Distributor**

Opposite of a multiplexer 1 to N demultiplexer 1 data input N data outputs Log2(n) control inputs This circuit will “connect” a data input to one and only one output. The selected output is specified by a decoding of the control inputs.

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**Example: 1 to 4 DeMUX Truth Table**

F3 F2 F1 F0 1 d = don’t care / Di = data on input i

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1 to 4 DeMUX Equations D is the DATA inputs, AB are control inputs and called the “select” lines.

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**1 to 4 DEMUX Circuit Only one F will be 2x4 Decoder active**

Only 1 AND gate will be “ON”

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1 to 4 DEMUX Symbol Selected Lines Outputs Data Input

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Example Design a 3x8 decoder using only 2x4 decoders and NOT gates.

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Solution “On” when A=0 “On” when A=1

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TPS Quiz

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**Basic Arithmetic Elements**

Half Adder

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**Half Adder-Truth Table**

S=A+B (arithmetic sum) A B S1 S0 1

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Half Adder Circuit

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**Full Adder-Truth Table**

S=A+B+C (arithmetic sum) A B C S1 S0 1 A B C S1 S0 1

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Full Adder You can show!!!

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Synthesis Logic Equation Logic Circuit

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Synthesis Logic Equation Logic Circuit

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**Synthesis Full Adder Circuit**

B S(0) C S(1) S(0) S(1) Simulation

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**Verification We verify the circuit via a simulation Logic Simulation**

Inputs S(0) S(1) S Outputs

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Verification Summary A B S(0) C S(1) Circuit S(0) S(1) Simulation

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Documentation A B S(0) C S(1) FullAdder C A B S(0) S(1) Block Diagram

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Ripple Carry Adder

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**Conceptualization 1111 11110 For the “worst case” we need to add**

4-bit adder (worst case) 1 1 1 1111 11110 For the “worst case” we need to add three bits to generate a single output bit with a possible carry out. Can we use our single bit adder for this?

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Ripple Carry Adder We can cascade several full adders to create a ripple carry adder The circuit gets its name because the carry bit “ripples” from one bit position to the next

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**Conceptualization First, let’s look at two bits What about the carry?**

FullAdder C A B S(0) S(1) B(1) Sum(1) A(0) FullAdder C A B S(0) S(1) B(0) Sum(0) What about the carry?

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**Conceptualization Let’s connect the two full adders**

B S(0) S(1) B(1) S(1) Cin A(0) Cout FullAdder C A B S(0) S(1) B(0) S(0) Set carry in for first bit to 0. Why?

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**Analysis Let’s test this for a few cases: 00 000 Correct!!!**

FullAdder C A B S(0) S(1) 00 000 FullAdder C A B S(0) S(1) Correct!!! Rule of thumb: Always test simple cases first!!

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**Analysis Let’s test this for the a few cases 11 110 Correct!!! 1 1**

FullAdder C A B S(0) S(1) 1 1 11 110 1 1 FullAdder C A B S(0) S(1) Correct!!!

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**Analysis Let’s test this for the a few cases 01 010 Correct!!!**

FullAdder C A B S(0) S(1) 1 1 01 010 1 1 FullAdder C A B S(0) S(1) 1 Correct!!!

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**Four Bit “Ripple” Adder**

Carry out Carry in

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Logic Simulation

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**8-bit Ripple Carry Adder**

Use two 4-bit adders

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**16-bit Ripple Carry Adder**

Use two 8-bit adders

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Subtraction Circuit

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Subtraction Circuit Calculate 2’s complement of B Add –B to A

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Add/Sub Circuit

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**Add/Sub Circuit Module**

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**Function Table for Add/Sub Module**

Functional Result S=A+B 1 S=A-B Add is a control input. It is active low. This means that the module will compute A+B when Add=0. It will compute A-B when Add=1.

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Add/Sub Circuit Design using Modules

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Add/Sub Circuit

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Add/Sub Circuit Add operation. Add=0

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Add/Sub Circuit Sub operation. Add=1 1 1

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TPS Quiz 17-18

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**Overflow/Underflow Detection**

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**Numerical Overflow/Underflow**

2’s complement number We have S=A+B Range of sum Overflow occurs if Underflow occurs if

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**Example: Overflow Let n=4, Range is**

Let A=$7, B=$7, then S=$7+$7=$E, but $E=%1110 = -2, so Overflow has occurred.

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**Example: Overflow -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7**

Let’s examine this more closely -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7 +7 8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7 So, overflow is the same as “wrap around.”

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**Example: Underflow Let n=4, let A=-7 and B=-7,**

in 2’s complement, A=B=$9, S=$9+$9=$12=$02 so underflow has occurred.

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**Example: Underflow -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7**

Let’s examine this more closely -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7 +1 +6 So, underflow is the same as “wrap around.”

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**Overflow/Underflow Detection**

How do we detect overflow and underflow? First adding a positive to a negative number is always OK. 4 bit example: 7 + (-8) = -1 Let’s examine the sum of the MSB’s to determine overflow and underflow. Set V=1, if overflow/underflow occurs

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**Examination of MSB b a cin S Co V Explanation A+B < 2n-1 (OK) 1**

a,b are the MSBs of A and B. cin is carry in; cout=carry out b a cin S Co V Explanation A+B < 2n-1 (OK) 1 A+B>2n-1 -1 (overflow) -A+B (OK) A-B (OK) -A-B< -2n-1 (underflow) -A-B > -2n-1 (OK)

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**Overflow/Underflow Detection**

We find

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**Overflow/Underflow Detection**

You can also use That is, if for the MSB carry_in is not equal to carry_out, overflow or underflow has occurred.

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TPS Quiz 19-20

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Comparators

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**F0 = (A = B) Equal Comparator**

Design a logic circuit which will compute F0 = (A = B)

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**2-bit Equal Comparator Truth Table**

F0 1

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**2-bit Equal Comparator Truth Table**

F0 1

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Solution You can show,

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**N-bit Equal Comparator**

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**F = (A = B) F = (A <> B) Not Equal Comparator**

Design a logic circuit which will compute F = (A <> B) F = (A = B) i.e. Just invert our Equal Comparator circuit

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**F2 = (A>B) F1 = (A<B) Magnitude Comparator**

Design a logic circuit which will compute F2 = (A>B) F1 = (A<B) Let’s develop a truth table for 2-bits

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**2-bit Magnitude (unsigned) Comparator Truth Table**

F2 F1 1

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**2-bit Magnitude (unsigned) Comparator Truth Table**

F2 F1 1

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You can show

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TPS Quiz 21

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**Arithmetic Logic Units (ALUs)**

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**Arithmetic Logic Unit (ALU)**

A,B are data inputs of n bits each in depth S is a control input. We have 2m operations F is the output

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**Example Let n=4,m=3 We have A[3..0] and B[3..0]**

With m=3, we have 23 = 8 operations Let’s look at a possible function table

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**Function Table s2 s1 s0 Function F=AB 1 F=A+B (logical OR) F=NOT A**

F=AB 1 F=A+B (logical OR) F=NOT A F=A XOR B F=A+B (Arithmetic) F=A-B F=A + 1 F=A - 1

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**Design using a Truth Table**

How large is the truth table? 2n from data inputs A and B Example: n=8, we have 16 data inputs A[7..0] and B[7..0] 3 control inputs Total of 2n+3 inputs N=8, we have 19 inputs Our truth table will have 192 (361) rows and 8 outputs Too complex. Let’s explore another alternative using a “system” or modular approach

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**Design using Modules Note: For S2=0, we have logic operations**

For S2=1, we have arithmetic operations So, let’s use S2 to control a 2x1 MUX to select between logic and arithmetic operations, so our top level design would look like:

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ALU Design

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ALU Design S2=0 With S2=0, F is the output from the logic module

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ALU Design S2=1 With S2=1, F is the output from the arithmetic module

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Logic Module Design

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**Function Table for Logic Module**

S2=0 s2 s1 s0 Function F=AB 1 F=A+B (logical OR) F=NOT A F=A XOR B We can use a 4x1 mux to implement this module

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Logic Module Design

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Logic Module Design F=AB AND Operation S[1..0]=00 0 0

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Logic Module Design F=A+B OR Operation S[1..0]=01 0 1

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Logic Module Design F=A NOT Operation S[1..0]=10 1 0

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Logic Module Design F=A XOR B XOR Operation S[1..0]=11 1 1

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**What do these logic modules look like?**

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AND Module

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OR Module

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NOT Module A F

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XOR Module

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**Let’s use our ADD/SUB Module**

Arithmetic Module Let’s use our ADD/SUB Module

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**Add/Sub Circuit Module**

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**Function Table for Arithmetic Ops**

1 F=A+B (Arithmetic) F=A-B F=A + 1 F=A - 1 Note: S0 can be use to indicate Addition or Subtraction. S1 can be use to indicate the B data input

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**Arithmetic Module Design**

B A S

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**Arithmetic Module Design**

B A S F=A+B S[1..0]=00

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**Arithmetic Module Design**

B A S F=A-B S[1..0]=01 1

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**Arithmetic Module Design**

B A S F=A+1 S[1..0]=10 1

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**Arithmetic Module Design**

B A S F=A-1 S[1..0]=11 1 1

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Overall Design We have

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ALU Design

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Logic Module Design

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**Arithmetic Module Design**

B A S

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Total Design Logic Module Arithmetic Module

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End of Chapter 4

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