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Chapter 4 Modular Combinational Logic

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Decoders

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n to 2 n decoder n inputs 2 n outputs For each input, one and only one output will be active. Uses: “Minterm generator” Wordline (memory) circuit Code conversion Routing data

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2 to 4 Decoder Example

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2 to 4 Decoder – Truth Table 2 to 4 decoder X1X0Y3Y2Y1Y

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2 to 4 Decoder Equations

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2 to 4 Decoder: Circuit

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2 to 4 Decoder: Block Symbol Symbol Circuit

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3 to 8 Decoder Example

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3 to 8 Decoder – Truth Table x2x1x0y7y6y5y4y3y2y1y

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3 to 8 Decoder Equations

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3 to 8 Decoder: Circuit

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3 to 8 Decoder: Block Symbol Symbol Circuit

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Design Example

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Example Using only a 3x8 decoder and two- input OR gates, design a logic circuit which implements the following Boolean equation

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Solution m2 m4 m5

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2 to 4 Decoder with Enable

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2x4 Decoder with Enable Enable is abbreviated as EN EN is called a Control Signal Control Signals can be Active High Signal EN = 1 – Turns “ON” Decoder Active Low Signal EN=0 – Turns “ON” Decoder

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2 x 4 Decoder with Active High Enable – Truth Table Enx1x0y3y2y1y

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2 to 4 Decoder with Enable Equations

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2 to 4 Decoder with Enable Circuit

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2 to 4 Decoder with Enable Symbol

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2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation) Enx1x0y3y2y1y0 0dd d = don’t care En has “highest” priority. If En=0, we “don’t care” about x1 or x0 because Y=0

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2 x 4 Decoder with Active Low Enable – Truth Table (Short hand notation) EnLx1x0y3y2y1y0 1dd d = don’t care En has “highest” priority. If En=1, we “don’t care” about x1 or x0 because Y=0

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2 to 4 Decoder with Active Low Enable Circuit

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Design Example

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Example Design a 3x8 decoder using only 2x4 decoders and NOT gates.

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Solution “On” when A=1 “On” when A=0

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TPS Quiz

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Encoders

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Opposite of a decoder 2 n to n encoder 2 n inputs n outputs For each input, the circuit will produce an “encoded” output

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Example: 4 to 2 Binary Encoder Truth Table X3X2X1X0Y1Y Assume only one input high at a time!!

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4 to 2 Encoder Equations

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Problems with initial design Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1? A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low.

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Problems with initial design If IA = 1 => all lines are 0 If IA = 0 => at least one line is 1 Q: What happens if more than one input is high at the same time? A: Design a “priority” encoder that will encode the input with the highest priority. Let’s set X3 with the highest priority, followed by X2, X1, and X0

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Example: 4 to 2 Priority Binary Encoder Truth Table X3X2X1X0Y1Y d01 01dd10 1ddd11

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Solution Y1 Y

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4 to 2 Priority Encoder Equations

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Multiplexer/Data Selectors MUX Very Important Module!!!

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Multiplexer(MUX)/Data Selector N to 1 multiplexer n data input lines Log 2 (n) control inputs One output This circuit will “connect” the selected input to the output. The selected input is specified by a decoding of the control inputs.

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Example: 4 to 1 MUX Truth Table D3D2D1D0ABF ddd 00 ddD1d01 dD2dd10 D3ddd11 d = don’t care / Di = data on input i Data Inputs Control Inputs Output

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4 to 1 MUX Equation D’s are the DATA inputs, AB are control inputs and called the “select” lines.

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4 to 1 MUX Circuit 2x4 Decoder Only a single AND gate will be “ON” at a time. Output Control Inputs Data Inputs

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4 to 1 MUX Symbol Data Inputs Control Inputs Output

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Data and Control Paths Logic Data Path Inputs Data Path Outputs Control Path Inputs Control Path Outputs

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MUX Applications

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Example Using a 4x1 MUX, design a logic circuit which implements: We have, Y

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Example Using a 4x1 MUX, design a logic circuit which implements: abYDn 000D0 011D1 101D2 110D3

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Solution

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Multibit Multiplexers

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Multi-bit Multiplexers J-bit nx1 mux sel d0 d1 … dn-1 d2 F J bits deep log 2 n J bits deep j=0 to 3 This is just J separate nx1 multiplexers

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Example 4-bit 4x1 MUX A B D0[3..0] D1[3..0] D3[3..0] D2[3..0] F[3..0]4 bits deep D0[3..0] D1[3..0] D2[3..0] D3[3..0] AB F[3..0] j=0 to 3 This is just 4 separate 4x1 muxes

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Example 4-bit 4x1 MUX Bit 0 Bit 3 Bit 2 Bit 1

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Example 4 bit 4x1 MUX For the jth output, we have D0[j] D1[j] D2[j] D3[j] A B F[j]

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Example 4 bit 4x1 MUX For the bit 0 output, we have D0[0] D1[0] D2[0] D3[0] A B F[0]

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Example 4 bit 4x1 MUX For the bit 1 output, we have D0[1] D1[1] D2[1] D3[1] A B F[1]

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Example 4 bit 4x1 MUX For the bit 2 output, we have D0[2] D1[2] D2[2] D3[2] A B F[2]

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Example 4 bit 4x1 MUX For the bit 3 output, we have D0[3] D1[3] D2[3] D3[3] A B F[3]

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Example 4 bit 4x1 Mux F[0] F[1] F[2] F[3] Complete Circuit Bit 0 Bit 1 Bit 2 Bit 3

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Example 4 bit 4x1 MUX Symbol

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Design Example Using a 4bit 4x1 MUX, design a 8bit 4x1 MUX

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Solution

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DeMultiplexers/ Data Distributors

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Demultiplexer/Data Distributor Opposite of a multiplexer 1 to N demultiplexer 1 data input N data outputs Log 2 (n) control inputs This circuit will “connect” a data input to one and only one output. The selected output is specified by a decoding of the control inputs.

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Example: 1 to 4 DeMUX Truth Table DABF3F2F1F0 D00000D D0100D0 D100D00 D11D000 d = don’t care / Di = data on input i

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1 to 4 DeMUX Equations D is the DATA inputs, AB are control inputs and called the “select” lines.

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1 to 4 DEMUX Circuit Only 1 AND gate will be “ON” 2x4 Decoder Only one F will be active

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1 to 4 DEMUX Symbol Data Input Selected Lines Outputs

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Example Design a 3x8 decoder using only 2x4 decoders and NOT gates.

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Solution “On” when A=1 “On” when A=0

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TPS Quiz

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Basic Arithmetic Elements Half Adder

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Half Adder-Truth Table S=A+B (arithmetic sum) ABS1S

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Half Adder Circuit

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Full Adder-Truth Table S=A+B+C (arithmetic sum) ABCS1S ABCS1S

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Full Adder You can show!!!

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Synthesis Logic Equation Logic Circuit

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Synthesis Logic Equation Logic Circuit

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Synthesis Full Adder Circuit S(0) S(1) C A B S(0) S(1) Simulation

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Verification S(0) S(1) We verify the circuit via a simulation Logic Simulation Inputs Outputs S

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Verification Summary S(0) S(1) C A B S(0) S(1) Simulation Circuit

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Documentation S(0) S(1) C A B FullAdder C A B S(0) S(1) Block Diagram

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Ripple Carry Adder

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Conceptualization 4-bit adder (worst case) For the “worst case” we need to add three bits to generate a single output bit with a possible carry out. Can we use our single bit adder for this?

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Ripple Carry Adder We can cascade several full adders to create a ripple carry adder The circuit gets its name because the carry bit “ripples” from one bit position to the next

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Conceptualization FullAdder C A B S(0) S(1) FullAdder C A B S(0) S(1) First, let’s look at two bits A(0) B(0) B(1) A(1) Sum(0) Sum(1) What about the carry?

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Conceptualization FullAdder C A B S(0) S(1) FullAdder C A B S(0) S(1) Let’s connect the two full adders A(0) B(0) B(1) A(1) S(0) S(1) Set carry in for first bit to 0. Why? Cout Cin 0

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Analysis FullAdder C A B S(0) S(1) FullAdder C A B S(0) S(1) Let’s test this for a few cases: Correct!!! Rule of thumb: Always test simple cases first!!

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Analysis FullAdder C A B S(0) S(1) FullAdder C A B S(0) S(1) Let’s test this for the a few cases Correct!!!

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Analysis FullAdder C A B S(0) S(1) FullAdder C A B S(0) S(1) Let’s test this for the a few cases Correct!!!

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Four Bit “Ripple” Adder Carry in Carry out

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Logic Simulation

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8-bit Ripple Carry Adder Use two 4-bit adders

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16-bit Ripple Carry Adder Use two 8-bit adders

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Subtraction Circuit

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Calculate 2’s complement of B Add –B to A

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Add/Sub Circuit

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Add/Sub Circuit Module

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Function Table for Add/Sub Module AddFunctional Result 0S=A+B 1S=A-B Add is a control input. It is active low. This means that the module will compute A+B when Add=0. It will compute A-B when Add=1.

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Add/Sub Circuit Design using Modules

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Add/Sub Circuit

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Add operation. Add=0 00

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Add/Sub Circuit Sub operation. Add=1 11

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TPS Quiz 17-18

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Overflow/Underflow Detection

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Numerical Overflow/Underflow 2’s complement number We have S=A+B Range of sum Overflow occurs if Underflow occurs if

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Example: Overflow Let n=4, Range is Let A=$7, B=$7, then S=$7+$7=$E, but $E=%1110 = -2, so Overflow has occurred.

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Example: Overflow Let’s examine this more closely -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7 +7 So, overflow is the same as “wrap around.” 8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7

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Example: Underflow Let n=4, let A=-7 and B=-7, in 2’s complement, A=B=$9, S=$9+$9=$12=$02 so underflow has occurred.

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Example: Underflow Let’s examine this more closely -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7 +6 So, underflow is the same as “wrap around.” +1

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Overflow/Underflow Detection How do we detect overflow and underflow? First adding a positive to a negative number is always OK. 4 bit example: 7 + (-8) = -1 Let’s examine the sum of the MSB’s to determine overflow and underflow. Set V=1, if overflow/underflow occurs

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Examination of MSB bacinSCoVExplanation A+B < 2 n-1 (OK) A+B>2 n-1 -1 (overflow) A+B (OK) A-B (OK) A-B< -2 n-1 (underflow) A-B > -2 n-1 (OK) a,b are the MSBs of A and B. cin is carry in; cout=carry out

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Overflow/Underflow Detection We find

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Overflow/Underflow Detection You can also use That is, if for the MSB carry_in is not equal to carry_out, overflow or underflow has occurred.

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TPS Quiz 19-20

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Comparators

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Equal Comparator Design a logic circuit which will compute F0 = (A = B)

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2-bit Equal Comparator Truth Table b1b0a1a0F

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2-bit Equal Comparator Truth Table b1b0a1a0F

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Solution You can show,

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N-bit Equal Comparator

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Not Equal Comparator Design a logic circuit which will compute F = (A <> B) F = (A = B) i.e. Just invert our Equal Comparator circuit

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Magnitude Comparator Design a logic circuit which will compute F2 = (A>B) F1 = (A**
**

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2-bit Magnitude (unsigned) Comparator Truth Table b1b0a1a0F2F

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2-bit Magnitude (unsigned) Comparator Truth Table b1b0a1a0F2F

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You can show

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TPS Quiz 21

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Arithmetic Logic Units (ALUs)

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Arithmetic Logic Unit (ALU) A,B are data inputs of n bits each in depth S is a control input. We have 2 m operations F is the output

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Example Let n=4,m=3 We have A[3..0] and B[3..0] With m=3, we have 2 3 = 8 operations Let’s look at a possible function table

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Function Table s2s1s0Function 000F=AB 001F=A+B (logical OR) 010F=NOT A 011F=A XOR B 100F=A+B (Arithmetic) 101F=A-B 110F=A F=A - 1

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Design using a Truth Table How large is the truth table? 2n from data inputs A and B Example: n=8, we have 16 data inputs A[7..0] and B[7..0] 3 control inputs Total of 2n+3 inputs N=8, we have 19 inputs Our truth table will have 19 2 (361) rows and 8 outputs Too complex. Let’s explore another alternative using a “system” or modular approach

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Design using Modules Note: For S2=0, we have logic operations For S2=1, we have arithmetic operations So, let’s use S2 to control a 2x1 MUX to select between logic and arithmetic operations, so our top level design would look like:

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ALU Design

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ALU Design S2=0 With S2=0, F is the output from the logic module

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ALU Design S2=1 With S2=1, F is the output from the arithmetic module

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Logic Module Design

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Function Table for Logic Module S2=0 s2s1s0Function 000F=AB 001F=A+B (logical OR) 010F=NOT A 011F=A XOR B We can use a 4x1 mux to implement this module

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Logic Module Design

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AND Operation S[1..0]=00 0 F=AB

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Logic Module Design OR Operation S[1..0]= F=A+B

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Logic Module Design NOT Operation S[1..0]= F=A

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Logic Module Design XOR Operation S[1..0]=11 1 F=A XOR B

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What do these logic modules look like?

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AND Module

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OR Module

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NOT Module AF

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XOR Module

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Arithmetic Module Let’s use our ADD/SUB Module

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Add/Sub Circuit Module

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Function Table for Arithmetic Ops s2s1s0Function 100F=A+B (Arithmetic) 101F=A-B 110F=A F=A - 1 Note: S0 can be use to indicate Addition or Subtraction. S1 can be use to indicate the B data input

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Arithmetic Module Design B A S

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B A S 0 0 F=A+B S[1..0]=00

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Arithmetic Module Design B A S 1 0 F=A-B S[1..0]=01

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Arithmetic Module Design B A S 0 1 F=A+1 S[1..0]=10

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Arithmetic Module Design B A S 1 1 F=A-1 S[1..0]=11

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Overall Design We have

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ALU Design

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Logic Module Design

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Arithmetic Module Design B A S

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Total Design Logic Module Arithmetic Module

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End of Chapter 4

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