34 Problems with initial design Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1?A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low.
35 Problems with initial design If IA = 1 => all lines are 0If IA = 0 => at least one line is 1Q: What happens if more than one input is high at the same time?A: Design a “priority” encoder that will encode the input with the highest priority.Let’s set X3 with the highest priority, followed by X2, X1, and X0
36 Example: 4 to 2 Priority Binary Encoder Truth Table 1d
39 Multiplexer/Data Selectors MUXVery Important Module!!!
40 Multiplexer(MUX)/Data Selector N to 1 multiplexern data input linesLog2(n) control inputsOne outputThis circuit will “connect” the selected input to the output. The selected input is specified by a decoding of the control inputs.
41 Example: 4 to 1 MUX Truth Table ControlInputsOutputData InputsD3D2D1D0ABFd1d = don’t care / Di = data on input i
42 4 to 1 MUX EquationD’s are the DATA inputs, AB are control inputs and calledthe “select” lines.
43 4 to 1 MUX Circuit Control Inputs Data Inputs Output 2x4 Decoder Only a single AND gate willbe “ON” at a time.
64 Demultiplexer/Data Distributor Opposite of a multiplexer1 to N demultiplexer1 data inputN data outputsLog2(n) control inputsThis circuit will “connect” a data input to one and only one output. The selected output is specified by a decoding of the control inputs.
65 Example: 1 to 4 DeMUX Truth Table F3F2F1F01d = don’t care / Di = data on input i
66 1 to 4 DeMUX EquationsD is the DATA inputs, AB are control inputs and calledthe “select” lines.
67 1 to 4 DEMUX Circuit Only one F will be 2x4 Decoder active Only 1 AND gate willbe “ON”
68 1 to 4 DEMUX SymbolSelectedLinesOutputsDataInput
69 ExampleDesign a 3x8 decoder using only 2x4 decoders and NOT gates.
84 Conceptualization 1111 11110 For the “worst case” we need to add 4-bit adder (worst case)111111111110For the “worst case” we need to addthree bits to generate a single output bitwith a possible carry out.Can we use our single bit adder for this?
85 Ripple Carry AdderWe can cascade several full adders to create a ripple carry adderThe circuit gets its name because the carry bit “ripples” from one bit position to the next
86 Conceptualization First, let’s look at two bits What about the carry? FullAdderCABS(0)S(1)B(1)Sum(1)A(0)FullAdderCABS(0)S(1)B(0)Sum(0)What about the carry?
87 Conceptualization Let’s connect the two full adders BS(0)S(1)B(1)S(1)CinA(0)CoutFullAdderCABS(0)S(1)B(0)S(0)Set carry in for first bit to 0. Why?
88 Analysis Let’s test this for a few cases: 00 000 Correct!!! FullAdderCABS(0)S(1)00000FullAdderCABS(0)S(1)Correct!!!Rule of thumb: Always test simple cases first!!
89 Analysis Let’s test this for the a few cases 11 110 Correct!!! 1 1 FullAdderCABS(0)S(1)111111011FullAdderCABS(0)S(1)Correct!!!
90 Analysis Let’s test this for the a few cases 01 010 Correct!!! FullAdderCABS(0)S(1)110101011FullAdderCABS(0)S(1)1Correct!!!
106 Numerical Overflow/Underflow 2’s complement numberWe have S=A+BRange of sumOverflow occurs ifUnderflow occurs if
107 Example: Overflow Let n=4, Range is Let A=$7, B=$7, then S=$7+$7=$E, but $E=%1110 = -2, so Overflow has occurred.
108 Example: Overflow -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7 Let’s examine this more closely-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7+78,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7So, overflow is the same as “wrap around.”
109 Example: Underflow Let n=4, let A=-7 and B=-7, in 2’s complement, A=B=$9, S=$9+$9=$12=$02so underflow has occurred.
110 Example: Underflow -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7 Let’s examine this more closely-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7+1+6So, underflow is the same as “wrap around.”
111 Overflow/Underflow Detection How do we detect overflow and underflow?First adding a positive to a negative number is always OK.4 bit example: 7 + (-8) = -1Let’s examine the sum of the MSB’s to determine overflow and underflow.Set V=1, if overflow/underflow occurs
112 Examination of MSB b a cin S Co V Explanation A+B < 2n-1 (OK) 1 a,b are the MSBs of A and B. cin is carry in; cout=carry outbacinSCoVExplanationA+B < 2n-1 (OK)1A+B>2n-1 -1 (overflow)-A+B (OK)A-B (OK)-A-B< -2n-1 (underflow)-A-B > -2n-1 (OK)
129 Arithmetic Logic Unit (ALU) A,B are data inputs of n bits each in depthS is a control input. We have 2m operationsF is the output
130 Example Let n=4,m=3 We have A[3..0] and B[3..0] With m=3, we have 23 = 8 operationsLet’s look at a possible function table
131 Function Table s2 s1 s0 Function F=AB 1 F=A+B (logical OR) F=NOT A F=AB1F=A+B (logical OR)F=NOT AF=A XOR BF=A+B (Arithmetic)F=A-BF=A + 1F=A - 1
132 Design using a Truth Table How large is the truth table?2n from data inputs A and BExample: n=8, we have 16 data inputsA[7..0] and B[7..0]3 control inputsTotal of 2n+3 inputsN=8, we have 19 inputsOur truth table will have192 (361) rows and 8 outputsToo complex. Let’s explore another alternative using a “system” or modular approach
133 Design using Modules Note: For S2=0, we have logic operations For S2=1, we have arithmetic operationsSo, let’s use S2 to control a 2x1 MUXto select between logic and arithmetic operations, so our top level design would look like:
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