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Lab 10 : Arithmetic Systems : Adder System Layout: Slide #2 Slide #3 Slide #4 Slide #5 Arithmetic Overflow: 2’s Complement Conversions: 8 Bit Adder/Subtractor System:

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Lab 10 : Adder system Layout : To demonstrate the process used by a digital adder system, two binary numbers will be added by hand. Add the 2 LSB’s. 1+1=10 (2 in binary) …or… 1+1 = 0 and a carry out of 1. Add Carry In + 1 + 0 = 10 Add 3 + 1 using four bit hand addition:0011 3 1 0001+ Carry Out of 1 0 1 0 1 Add Carry In + 0 + 0 = 01 1 0 Carry Out of 0 00 Ignore the Carry Out Add Carry In + 0 + 0 = 00 Answer = 4 A Cin B Cout S Adder systems are made up of modules called Full Adders. A + B + Cin (carry in) = S (sum) & Cout (carry out). A 4 bit adder requires 4 Full Adder modules. A Cin B Cout S A Cin B Cout S A Cin B Cout S Add 3 + 1 using the adder system : 0011 3 0001 1 A+B+Cin = S & Cout 1+1+0 = 0 and 1 1 0 A+B+Cin Cin must be connected to Cout A+B+Cin = S & Cout 1+0+1 = 0 and 1 1 0 A+B+Cin Cin must be connected to Cout A+B+Cin = S & Cout 0+0+1 = 1 and 0 A+B+Cin Cin must be connected to Cout 0 1 0 0 Answer =4 (0100) Full Adder Slide #2

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Lab 10: 2’s Complement Conversion : Signed numbers encoded using 2’s complement notation can be added and subtracted using one process: “The process of addition”. Converting numbers to 2’s complement form is easy. Positive Numbers: Example: Convert +22 into 8 bit 2’s complement form. Rule : 2’s complement notation = Binary Notation. 1248163264 Sign Bit Process: Write 22 as a 7 bit number. Make the Sign Bit =0 to denote a positive number and your done! 0010110 0+ 16+0+4+2 +0 = 22 0 Thus +22 = 0 0010110 in 8 bit 2’s complement notation. Negative Numbers: Example: Convert -22 into 8 bit 2’s complement form. Rule : 2’s complement notation is NOT= Binary Notation. You must use a 3 step procedure to convert the negative number. Step 1: Write –22 as an 8 bit positive number From the work above: +22 = 0 0010110 1248163264 Sign Bit 00010110 Step 2: Invert all bits The result of this process is called 1’s complement notation. 11101001 Step 3: Add 1 to this new binary pattern 11101001 + 1 11101010 Thus -22 = 1 1101010 in 8 bit 2’s complement notation. Theory: Adding a positive and a negative 2’s comp. number will subtract the 2 numbers. Test the Theory: Try 22+(-22) 11101010 00010110 + 00000000 -22 +22 1 At first glance it does not appear to work. The 1 in the MSB is actually a carry out and can be ignored! Answer = 0 Slide #3

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5 bit signed numbers will be used to demonstrate arithmetic overflow. The valid range of 5 bit numbers is –16 to +15. The range can be represented using a number line. Lab 10: Arithmetic Overflow : Arithmetic Overflow is an error that occurs when 2 numbers being added together generate an answer that requires more bits than are available for the answer. -16-14-12-10-8-6-4-20+2+4+6+8+10+12+15 Add 9+8. Each number on there own is a valid 5 bit number but there sum (17) exceeds the valid range. 901001 1248 Sign Bit 801000 + 10001 16 (2 4 ) –ve #s. 16 (2 4 ) +ve #s. The sum turns out to be a negative number. To check which negative number it is: invert and +1 and it will convert to its equivalent +ve number. If the error goes undetected then the system would calculate 9+8 = -15 Error! 10001 01110 + 1 0111115 Negative # Invert Add 1 Detecting Arithmetic Overflow errors is easy. All calculators and computers do it. Overflow never occurs if the 2 numbers being added have opposite sign bits. Think about it using the number line. One number on the positive side and the other on the negative side always generates a sum in between One number on this side Answer always falls in the middle NO overflow! Overflow may occur if the 2 numbers being added have the same sign bits. Think about it using the number line. Both numbers from the positive side may generate a sum that exceeds +15. Both numbers from the negative side may generate a sum that exceeds -16. Overflow from 2 positive numbers always wraps around to the negative end of the number line. In our example 9 + 8 = -15. 8+9-15 Overflow from 2 negative numbers always wraps around to the positive end of the number line. For example (–9) + (-8) = +15. (-9)+(-8)+15 An overflow detection system checks the logic level of each number’s sign bit. If they are the same then it checks the sign bit of the answer. If the sign bit of the answer is different than the sign bit of each number then overflow has occurred and the system generates an error message. Slide #4

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Lab 10: 8 Bit Adder/Subtractor : Two 4-bit adders are combined with XOR gates to create an 8-bit adder/subtractor system. The system will be used to add 12 + (-4) and then subtract 12 – (-4). Load the data registers with the 2 numbers: +12 and –4. 1248163264 Sign Bit 00011000+12 00001000+4 11110111Invert Add 111111001 11111001-4 00011000+12 Put the system in the ADD mode. ADD/SUB =0. The XOR gates are controlled inverters and will pass the number –4 to the adders. 0 11111001 00011000 Add the numbers and show the response at the S output of the adders. 0 1 Register B Register A 1100 1100 0C0 1000 1 C4 + 1000 1 1 1 Register B Register A 1111 0000 1C0 0000 C4 + 11 0000 1 Answer is 8 [12+(-4)] Put the system in the SUB mode. ADD/SUB =1. The XOR gates are controlled inverters and will pass the inverse of the number –4 to the adders. This will make the system subtract 12-(-4). 1 11 00 0 00 0 1 Add the numbers and show the response at the S output of the adders. 1 Register B Register A 0011 1100 1C0 0000 1 C4 + 1 1 0000 1 0 Register B Register A 0000 0000 1C0 0001 C4 + 0100 0 Answer is 16 [12-(-4)] Slide #5

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