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George Mason University Class Exercise 1A. 2 Rules If you believe that you know a correct answer, please raise your hand I will select one or more students.

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Presentation on theme: "George Mason University Class Exercise 1A. 2 Rules If you believe that you know a correct answer, please raise your hand I will select one or more students."— Presentation transcript:

1 George Mason University Class Exercise 1A

2 2 Rules If you believe that you know a correct answer, please raise your hand I will select one or more students (independently whether an answer given by the first student is correct or incorrect) Please, identify yourself by first name and give an answer Correct answer = 1 bonus point

3 Problem 1 List all 2-input logic gates that you can recall.

4 Problem 2 How many 2-input logic functions can be theoretically defined (whether they make sense or not)?

5 Problem 3 List all 1-input logic gates.

6 Problem 4 What is a minimum set of gates that can be used to implement all logic functions?

7 Problem 5 List four ways of expressing logic functions.

8 Problem 6 What are the De Morgan’s Laws? Write their equations and draw their schematic representation.

9 Problem 7 How many select inputs does an 8-to-1 MUX have? How many select inputs does an n-to-1 MUX have?

10 Problem 7 How many outputs does a decoder with two data inputs have? How many outputs does a decoder with n data inputs have?

11 Problem 8 Show how to implement a decoder that recognizes the following 4 ranges of a 16-bit address A, and generates the corresponding enable signals e0,e1,e2,e3: For A in:Assert C000-CFFF: e0 D000-DFFF: e1 E000-EFFF: e2 F000-FFFF: e3

12 Problem 9 How many inputs does an encoder with two data outputs have? How many inputs does an encoder with n data outputs have?

13 Problem 10 What is a difference between encoder and priority encoder?

14 Problem 11 Show how to implement Priority Encoder using multiplexers and a minimum number of logic gates

15 Problem 12 What is a difference between an adder, half-adder, and full-adder?

16 Problem 13 Show how to implement Full Adder using 8-to-1 multiplexers only

17 Problem 14 Show how to implement Full Adder using 4-to-1 multiplexers and inverters only

18 Problem 15 What is the width of an output of a 4x4 unsigned multiplier? What is the width of an output of a 4x4 signed multiplier? What is the width of an output of a NxN unsigned multiplier?

19 Problem 16 What is the width of an output of a 4x8 unsigned multiplier? What is the width of an output of a 4x8 signed multiplier? What is the width of an output of a NxM unsigned multiplier?

20 Problem 17 Give an example of binary inputs to an unsigned 4x4 multiplier and a signed 4x4 multiplier that produce different results.

21 Problem 18 Explain how to perform the following operations A. Z = X+Y mod 2 4 B. Z = X*Y mod 2 4 using a 4-bit adder with carry in (cin) and carry out (cout), and a 4x4 multiplier, respectively, where X, Y, and Z are 4-bit variables.

22 Explain how to perform the following operation using simple arithmetic and logic circuits: Y = (X*(2X + 1)) mod 2 4, where X and Y are 4-bit variables. Problem 19

23 Explain using simple diagrams (based on medium-scale logic components) how to efficiently perform the following operations in hardware using combinational logic only A. C = A <<< 3 B. C = A <<< B, where A, B, and C are 8-bit variables. Problem 20

24 Problem 21 What is a size of a memory with a 4-bit address input and an 8-bit data output? What is a size of a memory with an m-bit address input and an n-bit data output?

25 Problem 22 Show how to implement Full Adder using ROM (diagram + contents of ROM)

26 Problem 23 Show how to implement a 3x3 squarer, implementing equation y = x 2, using ROM (diagram + contents of ROM).

27 Explain how to perform the following operation using a single-port ROM only: Y = (X*(2X + 1)) mod 2 8, where X and Y are 8-bit variables. Show the implementation as a ROM, including the width of the address input and the width of the data output, as well as the contents of memory locations with addresses 0, 1, 8 and 16. Problem 24

28 Problem 25 What is a function of a tri-state buffer?


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