Presentation on theme: "Digital System Design-II (CSEB312)"— Presentation transcript:
1Digital System Design-II (CSEB312) Verilog TutorialPart - 2
2TopicsSequential LogicMore Combinational LogicFinite State Machines
3Sequential LogicVerilog uses certain idioms to synthesize into latches, flip-flops and FSMsOther coding styles may simulate correctly but produce incorrect hardware
4Always Statement General Structure: (sensitivity list)statement;Whenever the event in the sensitivity list occurs, the statement is executed
5D Flip-Flopmodule flop(clk, d, q);input clk;input [3:0] d;output [3:0] q;reg [3:0] q;(posedge clk) beginq <= d; // read as “q gets d”endendmoduleAny output assigned in an always statement must be declared reg. In this case q is declared as regBeware: A variable declared reg is not necessarily a registered output.We will show examples of this later.
8D Flip-Flop with Enable module dff_en(input clk,input reset,input en,input [3:0] d,output reg [3:0] q);// asynchronous reset and enable(posedge clk, posedge reset)if (reset) q <= 4'b0;else if (en) q <= d;endmodule
9Latchmodule latch(input clk,input [3:0] d,output reg [3:0] q);(clk, d)if (clk) q <= d;endmoduleWarning: We won’t use latches in this course, but you might write code that inadvertently implies a latch.
10Other Behavioral Statements Statements that must be inside always statements:if / elsecase, casezReminder: Variables assigned in an always statement must be declared as reg (even if they’re not actually registered!)
11Combinational Logic using always // combinational logic using an always statementmodule gates(input [3:0] a, b,output reg [3:0] y1, y2, y3, y4, y5);(*)begin // need begin/end because there is// more than one statement in alwaysy1 = a & b; // ANDy2 = a | b; // ORy3 = a ^ b; // XORy4 = ~(a & b); // NANDy5 = ~(a | b); // NORendendmoduleThis hardware could be described with assign statements using fewer lines of code, so it’s better to use assign statements in this case.
13Combinational Logic using case In order for a case statement to imply combinational logic, all possible input combinations must be described by the HDL.Remember to use a default statement when necessary.
14Combinational Logic using casez module priority_casez(input [3:0] a,output reg [3:0] y);begincasez(a)4'b1???: y = 4'b1000; // ? = don’t care4'b01??: y = 4'b0100;4'b001?: y = 4'b0010;4'b0001: y = 4'b0001;default: y = 4'b0000;endcaseendendmodule
15Blocked vs. Non-Blocked Assignments Blocked Assignment: One statement completes before next one completed. Statements are sequential so the statement order makes a difference.Use = operatorNon-Blocked Assignment: Statements execute in parallel (so the order does not affect the outcome)Use <= operator
16Blocked vs. Non-Blocked Assignments Example: Shift Register (ref p 159) – Using blocked assignment statementsmodule shift_reg(E, A, rst, clk);output E;input A, rst, clk;reg A, B, C, D;(posedge clk or posedge rst) beginif (rst) beginA=0; B=0; C=0; D=0;endelseA = B;B = C;C = D;D = E;end # of ifend // of alwaysendmodule
17Rules for Signal Assignment Use (posedge clk) and nonblocking assignments to model synchronous sequential logic(posedge clk)q <= d; // nonblockingUse continuous assignments to model simple combinational logic.assign y = a & b;Use (*) and blocking assignments to model more complicated combinational logic where the always statement is helpful.Do not make assignments to the same signal in more than one always statement or continuous assignment statement.
18Finite State Machines (FSMs) Finite state machines are Synchronous sequential circuits drawn in a form as shown below.The name FSM is used because k registers (sets of flip-flops) can have 2n states.An FSM has M inputs, N outputs, and k bits of states.FSM receives a clock and may be a reset also.On each clock edge, the FSM moves to the next state.Two types of FSMs are: Mealy and Moore.
19Finite State Machines (FSMs) Besides registers, there are two combinational blocks in an FSM:Next state logicOutput logicSo in Verilog, we can three blocks of codenext state logicstate registeroutput logic
20FSM Example: Divide by 3The double circle indicates the reset state
21// ---- output logic ---- FSM in Verilogmodule divideby3FSM (input clk, input reset, output y); reg [1:0] state, nextstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; // ---- state register ---- (posedge clk, posedge reset) begin if (reset) state <= S0; else state <= nextstate; end end // always// ---- next state logic ----(*) begincase (state)S0: nextstate <= S1;S1: nextstate <= S2;S2: nextstate <= S0;default: nextstate <= S0;endcaseend // always// ---- output logic ----always (posedge clk) beginif (state = = S0)y = 1;elsey = 0;endmodule