Download presentation

Presentation is loading. Please wait.

Published byEssence Maxfield Modified about 1 year ago

1
Review for Exam 2 Using MUXs to implement logic Using ROMs to implement logic Timing Analysis The internal structure of flip-flops Flip-flop timings Rising and falling edge triggered flip-flops Counters and state machines Generating next state equations from counter sequences. Implementation using RS, D, T and JK flip-flops Reading state sequence from timing diagrams Determining next states from schematics Moore vs. Mealy Max frequency for a state machine Verilog code

2
Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 for AB=00, Z=0 0

3
Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 for AB=01, Z=1 1

4
Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 for AB=11, Z=C’ C’

5
Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 C’ 0

6
Implementing Logic Functions With Muxes An alternate method 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 C’ 0 Z = A’B + BC’ A=0 B=0 A=0 B=1 A=1 B=0 A=1 B=1 Z = C’ = 0 Z = C’ = 1 Z = C’ = 0 Z = C’ = C’

7
Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

8
Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

9
Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

10
Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

11
Timing Analysis A B AB E C D CD F E+F X

12
Timing Analysis A B AB E C D CD F E+F X

13
Timing Analysis A B AB E C D CD F E+F X

14
Timing Analysis A B AB E C D CD F E+F X

15
Timing Analysis A B AB E C D CD F E+F X

16
Timing Analysis A B AB E C D CD F E+F X

17
Timing Analysis A B AB E C D CD F E+F X

18
The internal structure of flip-flops R S Q Q’ GATE GS GR D Q’ Q GATE D CLK Q Q’ D-type Flip-Flop

19
The internal structure of flip-flops T-type Flip-Flop CLK Q Q’ T

20
The internal structure of flip-flops JK-type Flip-Flop CLK Q Q’ J K

21
Flip-flop timings Clock-to-Q D CLK Q Q’ t CLK Q = t NOT + t AND + 2 x t NOR

22
CLK D Q t CLK Q time Flip-flop timings Clock-to-Q

23
D CLK Q Q’ t setup = t NOT + t AND + 2 x t NOR Flip-flop timings Setup time

24
CLK D Q t setup time Flip-flop timings Setup time

25
D CLK Q Q’ t hold = t NOT Flip-flop timings Hold time

26
CLK D Q t hold = t NOT time Clock edgeAND gate turns off, D can change Flip-flop timings Hold time

27
Flip Flop Timing CLK D Q t setup t hold t CLK Q time

28
D CLK Q Q’ Falling Edge Triggered DFF Rising and falling edge triggered flip-flops

29
Rising Edge Triggered DFF D CLK Q Q’ Rising and falling edge triggered flip-flops

30
Generating next state equations from counter sequences. Desired count sequence = … If current state = 00, next state = ????? Implemented count sequence = … N2 = Q2 Q1’ + Q1’ Q0 N1 = Q2 N0 = Q2’ Q0’ + Q1 Q0’

31
Implementation using RS, D, T and JK flip-flops

32
Reading state sequence from timing diagrams W X Y Z WXYZ = 0010, 0110, 0011, 0101, 1100, 1000, 1001, 1101, 1110, 0010

33
Determining next states from schematics Q0 Q2 CLK Q1 CLK Q2 D Q Q2 Q1’ Q0 Q2’ Q0’ Q1 Q0’ Q2 Q1 Q Initial state

34
Moore vs. Mealy

35
Max frequency for a state machine Steps:1. Determine the delay through the Flip Flops 2. Determine the delay through the IFL (max) 3. Add in setup time 4. Determine the smallest clock period possible 5. Max frequency = clock period

36
Structural Verilog Code and (output, input1, input2, ……); nand (output, input1, input2, ……); or (output, input1, input2, ……); nor (output, input1, input2, ……); not (output, input1); buf (output, input1); xor (output, input1, input2, ……); xnor (output, input1, input2, ……);

37
module mux21(q, sel, a, b); input sel, a, b; output q; wire selbar, a1, a2; not(selbar, sel); and(a1, selbar, a); and(a2, sel, b); or(q, a1, a2); endmodule a sel a1 b a2 q selbar Structural Verilog Code example

38
Dataflow Verilog Code

39
Dataflow Verilog Code example module mux21(q, sel, a, b); input sel, a, b; output q; assign q = (~sel & a) | (sel & b); endmodule module mux21(q, sel, a, b); input sel, a, b; output q; assign q = sel?b:a; endmodule OR

40
Verilog Code Heirarchy module mux41(q, sel, a, b, c, d); input[1:0] sel; input a, b, c, d; output q; wire tmp1, tmp2; mux21 M0(tmp1, sel[0], a, b); mux21 M1(tmp2, sel[0], c, d); mux21 M2(q, sel[1], tmp1, tmp2); endmodule a mux41 q bcd 2 sel mux21 sel[0] sel[1] ab cd q tmp1tmp2

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google