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ARM Processor. Why ARM? As of 2007, about 98% of the more than one billion mobile phones sold each year use at least one ARM processor. As of 2009,

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Presentation on theme: "ARM Processor. Why ARM? As of 2007, about 98% of the more than one billion mobile phones sold each year use at least one ARM processor. As of 2009,"— Presentation transcript:

1 ARM Processor


3 Why ARM? As of 2007, about 98% of the more than one billion mobile phones sold each year use at least one ARM processor. As of 2009, ARM processors account for approximately 90% of all embedded 32-bit RISC processors source:

4 History ARM was developed at Acron Computer Limited of Cambridge, England between 1983 and 1985 RISC concept introduced in 1980 at Stanford and Berkley ARM Limited founded in 1990 ARM Cores Licensed to partners to develop and fabricate new micro-controllers Soft-core

5 ARM Architecture Based upon RISC Architecture with enhancements to meet requirements of embedded applications A large uniform register file Load-store architecture, where data processing operations operate on register contents only Uniform and fixed length instructions 32-bit processor Instructions are 32-bit long Good Speed/Power Consumption Ratio High Code Density

6 Enhancement to Basic RISC Features Variable cycle execution for certain instructions load-store-multiple instructions Inline barrel shifter leading to more complex instructions Preprocessing one of the input registers before use Thumb 16-bit instruction set Code density improved by 30% over 32-bit instructions Enhanced DSP instructions Support fast 16x16 multiplier operations

7 Enhancement to Basic RISC Features Auto-increment and auto-decrement addressing modes to optimize program loops Load and Store Multiple instructions to maximize data throughput Conditional Execution of instruction to maximize execution throughput

8 ARM Architecture Versions Version 1 ( ) 26 bit addressing, no multiply or co-processor Version 2 Includes 32-bit result multiply co-processor Version 3 32 bit addressing Version 4 Add signed, unsigned half-word and signed byte load and store instructions Version 4T 16-bit Thumb compressed form of instruction introduced

9 ARM Architecture Versions Version 5T Superset of 4T adding new instructions Version 5TE Add signal processing signal extension Examples: ARM 6: v3 ARM 7: v3, ARM7TDMI: v4T StrongARM: v4 ARM 9E-S: v5TE

10 Overview: Core Data Path Data items are placed in register file No data processing instructions directly manipulate data in memory Instructions typically use two source registers and single result or destination registers A Barrel shifter on the data path can pre-process data before it enters ALU Increment/decrement logic can update register content for sequential access independent of ALU

11 Basic ARM Organization

12 General Purpose registers hold either data or address All registers are of 32 bits In user mode 16 data registers and 2 status registers are visible Data registers: r0 to r15 Three registers r13, r14, r15 perform special functions r13: stack pointer r14: link register r15: program counter Registers

13 Registers (2) Depending upon context, registers r13 and r14 can also be used as GPR Any instruction which use r0 can as well be used with any other GPR (r1-r13) (Orthogonal) In addition, there are two status registers CPSR: current program status register SPSR: saved program status register

14 Status Registers CPSR: monitors and controls internal operations

15 CPSR: Example

16 ARM Status Bits Every arithmetic, logical, or shifting operation sets CPSR bits: N (negative), Z (zero), C (carry), V (overflow). Example: = 0: NZCV = 0110.

17 Processor Modes Processor modes determine Which registers are active, and Access rights to CPSR register itself Each processor mode is either Privileged: full read-write access to the CPSR Non-privileged: read-only access to the control field of CPSR but read-write access to the condition flags

18 Processor Modes (2) ARM has seven modes Privileged: abort, fast interrupt request, interrupt request, supervisor, system and undefined Non-privileged: user User mode is used for programs and applications

19 Privileged Modes Abort when there is a failed attempt to access memory Fast Interrupt Request (FIQ) & interrupt request correspond to interrupt levels available on ARM Supervisor mode state after reset and generally the mode in which OS kernel executes

20 Privileged Modes (2) System mode special version of user mode that allows full read-write access of CPSR Undefined when processor encounters an undefined instruction

21 Processor Modes


23 Banked Registers Register file contains in all 37 registers 20 registers are hidden from program at different times These registers are called banked registers Banked registers are available only when the processor is in a particular mode Processor modes (other than system mode) have a set of associated banked registers that are subset of 16 registers Maps one-to-one onto a user mode register

24 Register Banking

25 SPSR Each privileged mode (except system mode) has associated with it, a Save Program Status Register or SPSR This SPSR is used to save the state of CPSR (Current Program Status Register) when the privileged mode is entered in order that the user state can be fully restored when the user process is resumed


27 Mode Changing Mode changes by writing directly to CPSR or by hardware when the processor responds to exception or interrupt To return to user mode a special return instruction is used that instructs the core to restore the original CPSR and banked registers

28 Mode Changing


30 Instructions Instructions process data held in registers and access memory with load and store instructions Classes of instructions: Data processing Branch instructions Load-store instructions Software interrupt instructions Program status register instructions

31 Features of ARM instruction set 3-address data processing instructions Conditional execution of every instruction Load and store multiple registers Shift, ALU operation in a single instruction

32 ARM data instructions Basic format: ADD r0,r1,r2 Computes r1+r2, stores in r0. Immediate operand: ADD r0,r1,#2 Computes r1+2, stores in r0.

33 Data Processing Manipulate data within registers MOVE instructions Arithmetic instructions Logical instructions Comparison instructions Suffix S on data processing instructions updates flags in CPSR

34 Data Processing Instructions Operands are 32-bit wide; come from registers or specified as literal (immediate operands) in the instruction itself Second operand sent to ALU via barrel shifter 32-bit result placed in register; long multiply instruction produces 64 bit result

35 Move instruction MOV Rd, N Rd: destination register N: can be an immediate value or source register Example: mov r7, r5 MVN Rd, N Move into Rd not (inverse) of the 32-bit value from source

36 Using Barrel Shifter Enables shifting 32-bit operand in one of the source registers left or right by a specific number of positions Basic Barrel shifter operations Shift left, shift right, rotate right Facilitates fast multiply, division and increases code density Example: mov r7, r5, LSL # 2 Multiplies content of r5 by 4 and puts result in r7

37 Using Barrel Shifter

38 Barrel Shift Instructions LSL, LSR : logical shift left/right fills with zeroes. ASL, ASR : arithmetic shift left/right fills with ones. ROR : rotate right RRX : rotate right extended with C performs 33-bit rotate, including C bit from CPSR above sign bit.

39 Barrel Shift with Carry

40 Arithmetic Instructions Implements 32 bit addition and subtraction 3-operand form Examples SUB r0, r1, r2 Subtract value stored in r2 from that of r1 and store in r0 SUBS r1, r1, #1 Subtract 1 from r1 and store result in r1 and update Z and C flags

41 Arithmetic Instructions ADD, ADC add (with carry) SUB, SBC subtract (with carry) RSB, RSC reverse subtract (with carry) MUL, MLA multiply (and accumulate)

42 Multiply Instructions Multiply contents of a pair of registers Long multiply generates 64 bit result Examples: MUL r0, r1, r2 Contents of r1 and r2 multiplied and put in r0 UMULL r0, r1, r2, r3 Unsigned multiply with result stored in r0 and r1 Number of cycles taken for execution of multiply instruction depends upon processor implementation

43 Multiply and Accumulate Result of multiplication can be accumulated with content of another register MLA Rd, Rm, Rs, Rn Rd = (Rm * Rs) + Rn UMLAL Rdlo, Rdhi, Rm, Rs [Rdhi, Rdlo] = [Rdhi, Rdlo] + (Rm * Rs)

44 Logical Instructions Bit-wise logical operations on the two source registers Operators: AND, OR, EOR (Ex-OR), BIC (bit clear) Example: BIC r0, r1, r2 r2 contains a binary pattern where every binary 1 in r2 clears a corresponding bit location in register r1 Useful in manipulating status flags and interrupt masks

45 With Barrel Shifter Use of barrel shifter with arithmetic and logical instructions increases the set of possible available operations Example: ADD r0, r1, r1 LSL # 1 Register r1 is shifted to the left by 1, then it is added with r1 and the result (3 times r1) is stored in r0.

46 Compare Instructions Enables comparison of 32 bit values Updates CPSR flags but do not affect other registers Examples CMP r0, r9 Flags set as a result of r0 – r9 TEQ r0, r9 Flags set as a result r0 ex-0r r9 TST r0, r9 Flags as a result of r0 & r9

47 Compare Instructions CMP : compare TST : bit-wise test TEQ : XOR These instructions set only the NZCV bits of CPSR.

48 Load-Store Instructions Transfers data between memory and processor registers Single register transfer Data types supported are signed and unsigned words (32 bits), half-words, bytes Multiple-register transfer Transfer multiple registers between memory and the processor in a single instruction Swap Swaps content of a memory location with the contents of a register

49 Single Transfer Instructions Load & Store data on a boundary alignment LDR, LDRH, LDRB: Load (word, half-word, byte) STR, STRH, STRB Store (word, half-word, byte) Supports different addressing modes: 3 primary addressing modes Preindex with writeback, Preindex, Postindex Almost 9 derived addressing modes Immediate, Register, Scaled register, …

50 Addressing Modes (1) Preindex with writeback LDR r0, [r1, #4]! Updates the address base register with new address

51 Addressing Modes (2) Preindex (Immediate Offset) LDR r0, [r1, #4] 12-bit offset added to the base register

52 Addressing Modes (3) Postindex LDR r0, [r1], #4 Updates the address register after address is used

53 Initial: r0 = 0x r1 = 0x mem32 [0x ] = 0x mem32 [0x ] = 0x Preindexing with writeback: LDR r0, [r1, #4]! r0 = 0x r1 = 0x Preindexing: LDR r0, [r1, #4] r0 = 0x r1 = 0x Example (1)

54 Example (2) Initial: r0 = 0x r1 = 0x mem32 [0x ] = 0x mem32 [0x ] = 0x Postindexing: LDR r0, [r1], #4 r0 = 0x r1 = 0x

55 Derived Addressing Modes Register indirect: LDR r0, [r1] Register operation: LDR r0, [r1, -r2] Calculated Address uses base register and another register Scaled: LDR r0, [r1, r2, LSL #2] Address is calculated using the base address register and a barrel shift operation

56 More Examples

57 Example: C assignments C: x = (a + b) - c; Assembler: ADR r4,a; get address for a LDR r0,[r4]; get value of a ADR r4,b; get address for b, reusing r4 LDR r1,[r4]; get value of b ADD r3,r0,r1; compute a+b ADR r4,c; get address for c LDR r2[r4]; get value of c

58 C assignment, cont’d. SUB r3,r3,r2; complete computation of x ADR r4,x; get address for x STR r3[r4]; store value of x

59 Example: C assignment C: y = a*(b+c); Assembler: ADR r4,b ; get address for b LDR r0,[r4] ; get value of b ADR r4,c ; get address for c LDR r1,[r4] ; get value of c ADD r2,r0,r1 ; compute partial result ADR r4,a ; get address for a LDR r0,[r4] ; get value of a

60 C assignment, cont’d. MUL r2,r2,r0 ; compute final value for y ADR r4,y ; get address for y STR r2,[r4] ; store y

61 Example: C assignment C: z = (a << 2) | (b & 15); Assembler: ADR r4,a ; get address for a LDR r0,[r4] ; get value of a MOV r0,r0,LSL 2 ; perform shift ADR r4,b ; get address for b LDR r1,[r4] ; get value of b AND r1,r1,#15 ; perform AND ORR r1,r0,r1 ; perform OR

62 C assignment, cont’d. ADR r4,z ; get address for z STR r1,[r4] ; store value for z

63 Multiple Register Transfer Load-store multiple instructions transfer multiple register contents between memory and the processor in a single instruction More efficient – for moving blocks of memory and saving and restoring context and stack These instructions can increase interrupt latency Usually instruction executions are not interrupted by ARM On ARM 7: 2 + Nt cycles N: number of registers to load t: number of cycles required for each sequential access to memory.

64 Multiple Byte Load-Store Any subset of current bank of registers can be transferred to memory or fetched from memory LDM STM Syntax: { } Rn{!}, {^} The base register Rn determines source or destination address

65 Address Modes (load-store multiple)

66 Load/Store Multiple Addressing

67 SWAP Instruction Special case of load store instruction Swap instructions: SWP: swap a word between memory and register SWPB: swap a byte between memory and register

68 SWAP Instruction Useful for implementing synchronization primitives like semaphore

69 Control Flow Instructions Branch Instructions Conditional Branches Conditional Execution Branch and Link Instructions Subroutine Return Instructions

70 Branch Instruction Branch instruction: B label Example: B forward Address label is stored in the instruction as a signed pc-relative offset Conditional Branch: B label Example: BNE loop Branch has a condition associated with it and executed if condition codes have the correct value

71 Example: Block memory copy Loop LDMIA r9!, {r0-r7} STMIA r10!, {r0-r7} CMP r9, r11 BNE Loop r9 points to source of data, r10 points to start of destination data, r11 points to end of the source

72 Conditional Execution An unusual feature of ARM instruction set is that conditional execution applies not only to branches but to all ARM instructions Example: ADDEQ r0, r1, r2 Instruction will only be executed when the zero flag is set to 1

73 Advantages Reduces the number of branches Reduces the number of pipeline flushes Improves performance of the code Increases code density Thumb Rule: Whenever the conditional sequence is 3 instructions or fewer (smaller and faster), exploit conditional execution than to use a branch

74 Branch & Link Instruction Perform a branch, save the address following the branch in the link register, r14 Example: BL subroutine For nested subroutine, push r14 and some work registers required to be saved onto a stack in memory Example: BL sub1 ……. STMFD r13!, {r0-r2, r14} BL sub2

75 Subroutine return instructions No specific instructions Example (1): sub …… MOV PC, r14 Example (2): when return address has been pushed to stack sub2 ….. LDMFD r13!, {r0-r12, PC}

76 Thumb Thumb encodes a subset of the 32 bit instruction set into a 16-bit subspace Thumb has higher performance than ARM on a processor with a 16-bit data bus Thumb has higher code density For memory constrained embedded system On average, a Thumb implementation takes 30% less memory than the equivalent ARM implementation. (source: ARM System Developer’s Guide)

77 Code density

78 Thumb Instruction Decoding Each Thumb instruction is related to a 32-bit ARM instruction.

79 ARMv5E Extensions Extensions to facilitate signal processing operations Supports Signed multiply accumulate instruction Greater flexibility and efficiency when manipulating 16 bit values for applications such as 16 bit digital audio processing.

80 Summary We have studied instruction set of ARM processors We discussed the use of barrel shifters We studied various addressing modes We have examined Thumb mode of operation

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