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ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 4.

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Presentation on theme: "ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 4."— Presentation transcript:

1 ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 4

2 Data movement instructions Shifter operands Special cases with PC as destination ARM7TDMI ISA Usage Conditional execution and flags updates Special cases of encoding Data Processing Instructions Memory Addressing Models and Modes Memory Allocation Allocation directives, alignment ARM7TDMI Load/Store Instructions Addressing modes Topics Complexity is our friend.

3 MOV Instruction Syntax MOV{ }{S}, RTL if (cond is true) Rd shifter_operand if((S==1) AND (Rd==R15)) CPSR SPSR Flags (if S is appended and Rd is not R15) N, Z, C (C is based on shifter operand) 313029282726252423222120191817161514131211109876543210 cond00I1101SSBZRdshifter operand

4 Shifter Operands Immediate (I=1) 8-bit value, 4-bit rotate code Signified by # Register No shift Shifted Register LSL, LSR, ASR, ROR Shift count from immediate or register Rotate Right with Extend Rotates register right 1 bit through CARRY flag

5 Conditional Execution and Flags If a condition is used, the instruction will only be executed if the condition is true.condition Flags are only updated if S is used Some instructions (B, BL, CMP, CMN, TST, TEQ, etc.) dont use S Using flags and conditions MOVS R1, R1 MOVR0, #1 MOVEQ R0, #0 MOVMI R0, #-1

6 MOV Special Cases If R15 is the destination of a MOV instruction and S is appended MOVS R15, R? In addition to the move into the PC, the CPSR is loaded from the current exception modes SPSR. Flags are not affected. This behavior is intended to only be used to return from exception modes. Do not do this in user or system mode – there is no SPSR and the results are unpredictable!

7 Specialized Moves MVN – move negated Shifter operand is complemented Note that this is a 1s-complement (NOT) MRS – move CPSR/SPSR to GP register MSR – move GP register to CPSR/SPSR SWP – swap SWPB – swap byte Swap instructions exchange values between memory and registers in an atomic operation

8 Data Processing Instructions The data processing instructions all use a very similar structure for operands, including a shifter operand Mnemonic{cond}{S} Rd, Rn, In general, Rd Rn operation shifter_operand The non-destructive instructions will not use a destination register (Rd). Some instructions reverse the operand order Since shifts can be part of any MOV or data processing instruction, there are no dedicated shift instructions.

9 Data Processing - Logical AND – bit-wise AND BIC – bit clear (bit-wise AND with complement of shifter operand) EOR – bit-wise exclusive-OR ORR – bit-wise inclusive-OR TEQ – test equivalence (non-destructive XOR) TST – test (non-destructive AND)

10 Data Processing - Arithmetic ADC – add with carry ADD – add CMN – compare negative CMP – compare RSB – reverse subtract RSC – reverse subtract with carry SBC – subtract with carry SUB - subtract

11 Multiply-Accumulate 32x32 multiplies - 32-bit result MLA – multiply-accumulate MUL – multiply 32x32 multiplies - 64-bit result SMLAL – signed long multiply-accumulate SMULL – signed long multiply UMLAL – unsigned long multiply-accumulate UMULL – unsigned long multiply

12 Memory Addressing Models Linear Memory Addressing Instructions can specify the complete address Segmented Memory Addressing Instructions do not contain the full address, just part of it (the offset) The remainder of the address is furnished by a page register or a segment register There may be multiple segment registers The full physical address is formed by combining the segment/page register and the offset from the instruction Advantages / disadvantages

13 Memory Addressing Modes Direct Addressing The operand address is encoded into the instruction. In variable length instructions, the full physical address can usually be encoded. In fixed length instructions, usually only the least significant part of the address can be encoded The remainder of the address can be set to 0 (base page addressing) The remainder of the address can be obtained from a page register or segment register.

14 Memory Addressing Modes (cont) Register Indirect Addressing The instruction specifies a register that contains the memory address to access May also support updating the register as part of the instruction (auto-increment, auto-decrement, etc.) Memory Indirect Addressing A memory location (encoded in the instruction) contains the address to transfer to/from

15 Memory Addressing Modes (cont) Indexed Addressing The physical address is calculated from a constant starting address (encoded in the instruction) and the contents of a register Typically used for accessing data in arrays Base address = array starting address Register holds (element index × element size) If byte array, element size = 1 If halfword array, element size = 2 If word array, element size = 4 The processor may do the index * element size calculation automatically

16 Based Addressing The physical address is calculated from a base address contained in a register, plus a constant offset encoded in the instruction Typically used for accessing information in data structures. Register holds starting address of structure. Offset is distance from the start of the structure to the desired structure element. Code can then access any instance of the structure just by changing register contents to point to it. Memory Addressing Modes (cont)

17 PC-Relative Addressing The address is computed by adding an offset value encoded in the instruction to the current value of the program counter. In many microprocessors, the PC is not part of the programmers model, so PC-relative addressing is considered distinct from indexed or based addressing. ARM will use PC-relative addressing to implement the appearance of direct addressing. Distance from the instruction to the label must be known at assembly-time. Memory Addressing Modes (cont)

18 ARM7TDMI Memory Allocation Memory operands Stored in little-endian format Data allocation directives DCB, DCW, DCD, SPACE, ALIGN Identifiers and initializers Constants vs. variables Arrays and strings Setting up a data area Read-write AREAs are all linked into SRAM Variable naming

19 ARM7 Memory Addressing Modes All ARM memory addressing modes use a base register Can also have a constant offset or use another register for the offset The second register can also be shifted The apparent ability to use direct addressing with the ARM will be obtained by using PC-relative addressing Will look at how ARM accomplishes this later The same idea will be used for the ADR pseudo-instruction

20 ARM7 Load/Store Instructions LDR/STR Load and store a 32-bit register Does not matter if signed or unsigned Address should be word-aligned LDRBLDRB/STRB Load and store an unsigned byte On load, the value is zero-padded to 32-bits

21 ARM7 Load/Store Addressing Base register +/- immediate offset Address = (Rn) +/- offset_12 Syntax: [Rn, +/-# ] Base register +/- register offset Address = (Rn) +/- (Rm) Syntax: [Rn, +/-Rm] Base register +/- shifted register offset Address = (Rn) +/- (shifted Rm) Shift modes with immediate shift count LSL, LSR, ASR, ROR, RRX Syntax: [Rn, +/-Rm, shift_mode #count] Rn is unaffected by these addressing modes

22 ARM7 Load/Store Addressing (cont) Pre-indexed Rn is updated with the calculated address Syntax: [Rn, +/-# ]! Syntax: [Rn, +/-Rm]! Syntax: [Rn, +/-Rm, shift_mode #count]! Post-indexed Rn is used as the transfer address. Then, Rn is updated with the calculated address Syntax: [Rn], +/-# Syntax: [Rn], +/-Rm Syntax: [Rn], +/-Rm, shift_mode #count

23 ARM7 Load/Store Instructions (cont) LDRSB/LDRSH Load a signed byte/halfword from memory Byte/halfword is sign-extended to 32-bits LDRH/STRH Load and store an unsigned halfword On load, the value is zero-padded to 32-bits The addressing modes are similar to LDR/STR, but are more restricted Base +/- offset_8 Base +/- register Pre-indexed and post-indexed

24 ARM7 Load/Store Multiple LDM/STM load and store multiple registers to memory in a single instruction Syntax: LDM{ }, {!}, Addressing mode options IA – Increment by 4 After transfer IB – Increment by 4 Before transfer DA – Decrement by 4 After transfer DB – Decrement by 4 Before transfer Register write-back controlled by ! Registers are always written/read from memory with lowest register number in the lowest address

25 ARM7 Memory Pseudo-Instructions Direct addressing (i.e. LDR R0, my_label) Encoded as LDR R0, [PC, #±offset] ADR (i.e. ADR R0, my_label) Encoded as ADD/SUB R0, PC, #number LDR – Load register LDR R0, =(expression) If expression is a legal immediate value, encodes as MOV/MVN Otherwise, allocates a word to store expression in, then loads from that word using LDR with PC-relative addressing LDR R0, =(label) Allocates a word to store the labels address in, then loads that word using LDR with PC-relative addressing

26 In-Class Exercise Create a source code template with a code area and a data area Allocate a 100 byte array Bytes in the data area Create a pointer aBytes to the array in the code area Declare a halfword variable HwVar in the data area and initialize to 0xAA55 Create a pointer aHwVar to HwVar in the code area Use byte transfers to set HwVar to 0xCC33 Copy HwVar into R0 as unsigned and R1 as signed Store the elements index into the 0 th, 50 th, and 100 th elements of the array If the 50 th element of the array is not zero, exchange the 0th and 100 th elements of the array References MOV instruction LDRB instruction SWAPB instruction ConditionsMOV instructionLDRB instructionSWAPB instructionConditions

27 Wrapping Up Reading for next week Chapter 6.12-6.13 Quiz #1 will be held Wednesday, 10/8 at 7:15pm in room TBA EH. Coverage will be over modules 1 and 2. Calculators are not permitted. You may have a 3x5 card with handwritten notes. The instruction set documentation will be provided. If you have a conflict, please send me the details by email.

28 c signed character uc unsigned character i integer ui unsigned integer si short integer li long integer n an integer number where the actual size is irrelevant f float d double s string of characters sz string of characters, terminated by a null character b an integer or character used as a boolean value by single byte ct an integer being used as a counter or tally p pointer to a structure or general void pointer px pointer to a variable of class x, e.g. pi, pf, pli Hungarian Notation

29 ARM7 Condition Codes Opcode [31:28] Mnemonic extensionMeaningCondition flag state 0000EQEqualZ==1 0001NENot equalZ==0 0010CS/HSCarry set / unsigned higher or sameC==1 0011CC/LOCarry clear / unsigned lowerC==0 0100MIMinus / negativeN==1 0101PLPlus / positive or zeroN==0 0110VSOverflowV==1 0111VCNo overflowV==0 1000HIUnsigned higher(C==1) AND (Z==0) 1001LSUnsigned lower or same(C==0) OR (Z==1) 1010GESigned greater than or equalN == V 1011LTSigned less thanN != V 1100GTSigned greater than(Z==0) AND (N==V) 1101LESigned less than or equal(Z==1) OR (N!=V) 1110ALAlways (unconditional)Not applicable 1111(NV)NeverObsolete, ARM7TDMI unpredictable

30 MOV Instruction Reference Syntax MOV{ }{S}, RTL if (cond is true) Rd shifter_operand if((S==1) AND (Rd==R15)) CPSR SPSR Flags (if S used and Rd is not R15) N, Z, C (C is based on shifter operand)

31 LDRB Instruction Reference Syntax LDRB{ }, RTL if (cond is true) Rd[7:0] memory[memory_address] Rd[31:8] 0 if(writeback) Rn end_address Flags None

32 SWPB Instruction Reference Syntax SWP{ }B,, [ ] RTL if (cond is true) temp (Rn) (Rn) Rm Rd temp Flags are not affected

33 Team ConcepTest What are the primary functions of an assembler? What sorts of errors might it detect? What are the primary functions of a linker? What sorts of errors might it detect?

34 One Minute Paper How do you feel that your homework team is functioning? Would you say that it is hindering, improving, or having no effect on your learning?

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