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Microprocessors. Functions of 68HC11 Microprocessor Providing tuning and control signal for all elements of microcomputer Providing tuning and control.

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Presentation on theme: "Microprocessors. Functions of 68HC11 Microprocessor Providing tuning and control signal for all elements of microcomputer Providing tuning and control."— Presentation transcript:

1 Microprocessors

2 Functions of 68HC11 Microprocessor Providing tuning and control signal for all elements of microcomputer Providing tuning and control signal for all elements of microcomputer Fetching instruction and data from memory Fetching instruction and data from memory Transferring data from memory Transferring data from memory Decoding instruction Decoding instruction Performing arithmetic and logic operations called for by instructions Performing arithmetic and logic operations called for by instructions Responding to I/O generated control signals such as reset and interrupt Responding to I/O generated control signals such as reset and interrupt

3 68 HC MPU 5 16 bit registers 5 16 bit registers 2 8 bit accumulators 2 8 bit accumulators 8 bit condition code registers 8 bit condition code registers Control bus signals are expandable Control bus signals are expandable

4 Timing and control section Control Bus signal Control Bus signal AS signal AS signal E clock E clock Reset Reset

5 Functions of reset Fetches the content of ROM address FFFE and loads into PC H Fetches the content of ROM address FFFE and loads into PC H Fetches the content of ROM address FFFF and load it into PC1 so that (PC) is now 2AC6 Fetches the content of ROM address FFFF and load it into PC1 so that (PC) is now 2AC6 Begin fetching and executing instruction at address 2AC6 Begin fetching and executing instruction at address 2AC6

6 Microprocessor common function Initialize MPU registers Initialize MPU registers Initialize I/O device control registers Initialize I/O device control registers Perform test on system RAM Perform test on system RAM Check status of I/O devices Check status of I/O devices Send messages to output devices Send messages to output devices

7 Instruction register When the MPU fetches an instruction word from memory it sends to the IR When the MPU fetches an instruction word from memory it sends to the IR

8 Program Counter (PC) Contains in the memory address of the next instruction code that the MPU is to fetch. Contains in the memory address of the next instruction code that the MPU is to fetch.

9 Accumulator Register that takes part in most of the operations performed by the ALU Register that takes part in most of the operations performed by the ALU It is also the register in which the result are being placed after most ALU operations It is also the register in which the result are being placed after most ALU operations The source of the operand and destination of the result The source of the operand and destination of the result

10 Data Address Register Memory address register Memory address register Address latching register Address latching register Used when executing ADD instruction Used when executing ADD instruction

11 General Purpose register GPR the accumulators can perform the function of a general purpose register in many programming situations. GPR the accumulators can perform the function of a general purpose register in many programming situations.

12 Common GPR instruction access codes Load GP from memory [M] > [GP] Load GP from memory [M] > [GP] Store GP in memory [GP] > [M] Store GP in memory [GP] > [M] Transfer contents of one GP register to another GP register : [GP1] > [GP2] Transfer contents of one GP register to another GP register : [GP1] > [GP2] Increment GP by 1: [GP +1 ] > [GP] Increment GP by 1: [GP +1 ] > [GP] Decrement GP by 1: [GP-1] > [GP] Decrement GP by 1: [GP-1] > [GP]

13 Start Load [GP] with value = COUNT Fron the memory Instruction Sequence to be Executed a number of times = COUNT Decrement [GP] [GP -1] > [GP] Is [GP] = 0? Next portion of program If [GP] =0 go to the next instruction in sequence Yes If [GP] not = 0 branch back to This set [GP] = COUNT Program Loop

14 Index register 68HC11 has two 16 bit index register (index register Y and index register X) 68HC11 has two 16 bit index register (index register Y and index register X) Similar to general purpose register Similar to general purpose register Its operation is called index addressing Its operation is called index addressing It holds address base C for X and Y index register It holds address base C for X and Y index register

15 Offset instruction illustration for register X Address Instruction code MnemonicDescription C000A6 LDAA $04,X Load accumulator A from address [X]+04. C00104 Offset byte Effective Address = offset + [X] = 04 + C450 = C454

16 Y register instruction illustration Y register instruction illustration Address Instruction code MnemonicDescription C00018 LDAA $04,Y Load accumulator A A6 from address [Y]+04. C00104 Offset byte Effective Address = offset + [Y] = 04 + C450 = C454

17 Important process during the operation Accumulator A and B are cleared to zero before any ADD operation occurs Accumulator A and B are cleared to zero before any ADD operation occurs Index register [X] is initially loaded with the number 2067 Index register [X] is initially loaded with the number 2067 Accumulator B is initially loaded with 07 which the number of memory locations to be added. ACCB is being used to count down the number of times that blocks 5-8 are executed Accumulator B is initially loaded with 07 which the number of memory locations to be added. ACCB is being used to count down the number of times that blocks 5-8 are executed Blocks 5-8 are executed a total of seven times before ACCB is decrement to 00 program goes to block 9 to store the final sum in memory location 2068 Blocks 5-8 are executed a total of seven times before ACCB is decrement to 00 program goes to block 9 to store the final sum in memory location 2068 The ADD operation (block 5) are executed using data from different address each time starting with 2067 and ending with 2061.this means the data is now loaded to the accumulator The ADD operation (block 5) are executed using data from different address each time starting with 2067 and ending with 2061.this means the data is now loaded to the accumulator

18 Start Is [ACCB]=0?HALT Clear [ACCA] Clear [ACCB] Load [X] with Value 2067 Load [ACCB] with value 07 Add data stored at address [X] +00 to [ACAA] Decrement [X] Decrement ACCB Store [ACCA] in memory location 2068 No

19 Condition Code register Consist of individual bits Consist of individual bits Each bits is called Flags Each bits is called Flags This is the 68HC11code register b7b6b5b4b3b2b1b0 SXHINZVC

20 Condition Code functions C – Carry flag reflects the carry status of arithmetic operation. C – Carry flag reflects the carry status of arithmetic operation. V – the overflow use to indicate overflow whenever signed numbers are being added or subtracted V – the overflow use to indicate overflow whenever signed numbers are being added or subtracted Z – zero flag is automatically set to 1 Z – zero flag is automatically set to 1 N – negative used to indicate any sign result of any arithmetic data manipulation N – negative used to indicate any sign result of any arithmetic data manipulation I- interrupt mask flag is used to indicate effects on the IRQ I- interrupt mask flag is used to indicate effects on the IRQ H – Half carry flag is change only by addition instruction H – Half carry flag is change only by addition instruction X – X interrupt mask used to indicate not XIRQ X – X interrupt mask used to indicate not XIRQ S – stop disable flag is used to prevent the stop instruction S – stop disable flag is used to prevent the stop instruction

21 Conditional branching It examine the value of the zero flag It examine the value of the zero flag If zero flag is = 0 If zero flag is = 0 The next instruction will be taken at a normal sequence The next instruction will be taken at a normal sequence If zero flag is = 1 If zero flag is = 1 The program will branch into new address for the next instruction The program will branch into new address for the next instruction If carry clear (BCC) or set booth will examine the carry flag If carry clear (BCC) or set booth will examine the carry flag

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27 Two operands operators Add Add Subtract Subtract

28 Accumulator and memory instructions

29 Load, Store and transfer instruction

30 Arithmetic operation instruction

31 Continuation..

32 Multiply and divide instruction

33 Logical operation instruction

34 Shift and rotate instructions

35 Stack and index register instruction

36 Condition code register instruction

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38 Branch instructions

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