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ARM CPU Internal I Prof. Taeweon Suh Computer Science Education Korea University.

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Presentation on theme: "ARM CPU Internal I Prof. Taeweon Suh Computer Science Education Korea University."— Presentation transcript:

1 ARM CPU Internal I Prof. Taeweon Suh Computer Science Education Korea University

2 Korea Univ Overview For the sake of your understanding, we simplify the CPU and its system structure 2 CPU North Bridge South Bridge Main Memory (DDR) FSB (Front-Side Bus) DMI (Direct Media I/F) Real-PC system Memory (Instruction, data) ARM CPU Address Bus Data Bus Simplified

3 Korea Univ Actual ARM Connection ARM CPU has separate connections to memory (caches) 3 ARM CPU core Instruction Cache Address Bus Data Bus Instruction fetch Data access Address Bus Data Bus Data Cache Memory Instruction/ Data access Address Bus Data Bus ARM920T

4 Korea Univ Overview Microarchitecture is composed of datapath and control Datapath operates on words of data Datapath elements are used to operate on or hold data within a processor Datapath elements include the register file, ALU, muxes, and memory Control tells the datapath how to execute instructions Control unit receives the current instruction from the datapath and tells the datapath how to execute that instruction Specifically, the control unit produces mux select, register enable, ALU control, and memory write signals to control the operation of the datapath Essential ARM instructions Data processing instructions: add, sub, cmp, and, or Memory access instructions: ldr, str Branch instructions: b, bl 4

5 Korea Univ Instruction Execution in CPU Generic steps of the instruction execution in CPU Fetch uses the program counter ( PC ) to supply the instruction address and fetch instruction from memory Decoding decodes instruction and reads operands Extract opcode: determine what operation should be done Extract operands: register numbers or immediate from fetched instruction Execution Use ALU to calculate (depending on instruction class) Arithmetic or logical result Memory address for load/store Branch target address Access memory for load/store Next Fetch PC target address or PC ARM CPU core Address Bus Data Bus Instruction/ Data Memory Fetch with PC Execute Address Bus Data Bus Decode PC = PC +4

6 Korea Univ ARM CPU core Instruction Fetch 6 PC Memory Address Out Add 4 32-bit register (flip-flops) Increment by 4 for the next instruction 32 instruction reset clock What is PC on reset in ARM? PC = 0x0000_0000

7 Korea Univ Memory Memory is classified into RAM (Random Access Memory) and ROM (Read-Only Memory) RAM is classified into DRAM (Dynamic RAM) and SRAM (Static RAM) DDR is a kind of DRAM DDR is a short form of DDR (Double Data Rate) SDRAM (Synchronous DRAM) DDR is used as main memory in modern computers 7

8 Korea Univ Simple ARM Test Code 8 assemble

9 Korea Univ Instruction Decoding 9 Instruction decoding separates the fetched instruction into the fields Opcode determines which operation the instruction wants to do Control logic should be designed to supply control signals to datapath elements (such as ALU and register file) Operands Register numbers in the instruction are sent to the register file Immediate field is either sign-extended or zero-extended depending on instructions* *It seems immediate is zero-extended in ARM case. If you write add r1, r2, #-12, assembler generates sub r1, r2, 12. The shifter operand could be logical (or arithmetic) shift right a register by immediate. In this case, the register is zero-filled or signed-filled in the shifted vacant bits

10 Korea Univ ARM CPU Schematic with Instruction Decoding 10 Memory Address Out 32 instruction PC Add 4 reset clock Register File Inst[15:12] (=Rd) Inst[19:16] (=Rn) Inst [3:0] (=Rm) Rn 32 Rm 32 wd 32 RegWrite R0 R1 R2 R3 R14 R15 (PC) … Control Unit Opcode 832 zero- extended imm RegWrite

11 Korea Univ Instruction Execution #1 11 Arithmetic and logical instructions Examples: add, adc, sub, sbc, cmp, mov, and, or … Two source operands One is always a register The other has two basic forms: Immediate or register (optionally shifted) sub r1, r2, r3 # r1 = r2 – r3 add r1, r2, r3 # r1 = r2 + r3 sub opcode: 0010 add opcode: 0100

12 Korea Univ Data Processing Instruction Formats 12 Source: ARM Architecture Reference Manual

13 Korea Univ ARM CPU Schematic with Instruction Execution #1 13 Memory Address Out 32 instruction PC Add 4 reset clock Register File Inst[15:12] (=Rd) Inst[19:16] (=Rn) Inst [3:0] (=Rm) Rn 32 Rm 32 wd 32 RegWrite R0 R1 R2 R3 R14 R15 (PC) … Control Unit opcode 832 zero- extended imm ALU mux ALUSrc RegWrite

14 Korea Univ Instruction Execution #2 14 Memory access instructions ldr, str instructions ldr R1, [R2, #4] // R1 <= [R2 + 4] str R1, [R2,R3] // [R2 + R3] <= R1

15 Korea Univ Memory Access Instruction Formats 15 Source: ARM Architecture Reference Manual Load and Store Word or Unsigned Byte instructions

16 Korea Univ ARM CPU Schematic with Instruction Execution #2 16 Memory Address Out 32 instruction PC Add 4 reset clock Register File Inst[15:12] (=Rd) Inst[19:16] (=Rn) Inst [3:0] (=Rm) Rn 32 Rm 32 wd 32 R0 R1 R2 R3 R30 R31 … Control Unit opcode 832 zero- extended imm ALU mux ALUSrc Memory Address ReadData WriteData MemWrite ALUSrc RegWrite MemWrite MemtoReg mux ldr R1, [R2, #4] // R1 <= [R2 + 4] str R1, [R2, R3] // [R2 + R3] <= R1 Rd 8-or or-12

17 Korea Univ Instruction Execution #3 17 Execution of the branch and jump instructions b, bl instructions b target (offset) Destination = (PC + 8) + sign-extend (imm << 2)

18 Korea Univ ARM CPU Schematic with Instruction Execution #3 ( B ) 18 Memory Address Out 32 instruction Register File Inst[15:12] (=Rd) Inst[19:16] (=Rn) Inst [3:0] (=Rm) Rn 32 Rm 32 wd 32 R0 R1 R2 R3 R14 R15 (PC) … Control Unit opcode 1232 zero- extended imm ALU mux ALUSrc Memory Address ReadData WriteData MemWrite MemtoReg mux Note that Branch Destination = (PC+8) + (sign-extend) (imm << 2)} 32 branch 24 imm Sign extension <<2 8-or-12 Rd PC Add 4 reset clock Add mux branch


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