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1 THUMB Instructions: Branching and Data Processing Thomas Clark, Charlie Phipps, Samir Thakral.

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Presentation on theme: "1 THUMB Instructions: Branching and Data Processing Thomas Clark, Charlie Phipps, Samir Thakral."— Presentation transcript:

1 1 THUMB Instructions: Branching and Data Processing Thomas Clark, Charlie Phipps, Samir Thakral

2 Outline □Review of THUMB Instruction Set □THUMB Branch Instructions □THUMB Data Processing Instructions □Conclusion/Wrap-up 2

3 THUMB Review 3

4 THUMB Instruction Set □ Compressed, 16-bit subset of the ARM instruction set □ Used to increase code density and in some cases, performance and power-efficiency □ Not a complete architecture: all processors that support THUMB also support ARM □ THUMB instructions have a restricted view of registers ■ Registers R0 through R7 are for general purpose use □ Most THUMB instructions are 2-address format, opposed to 3-address format in ARM 4

5 ARM vs. THUMB Comparison ARM □ 32-bit instruction set □ 3-data address instructions □ 16 general purpose registers □ More regular binary encoding THUMB □ 16-bit instruction set □ 2-data address instructions □ 8 general purpose registers □ Subset of ARM instructions □ Greater code density □ If used correctly, can lead to better performance/ power-efficiency 5

6 THUMB Branch Instructions 6

7 □Include various forms of PC-relative branch and branch and link instruction seen in ARM □Branch and Exchange instruction for switching between ARM and THUMB instruction sets □ARM instructions have a 24-bit offset field which will not fit in the 16-bit format. □THUMB instruction set includes various ways of subsetting the functionality. 7

8 THUMB Branch Instructions Typical use of branch instructions include: □Short conditional branches to control loop exit □Medium-range unconditional branches to ‘goto’ sections of the code □Long-range branches for subroutine calls 8

9 THUMB Branch Instructions 9

10 □First two formats show how the condition field is traded off against the offset length. □Condition field in the first format is the same as that in all the ARM instructions □The first two formats are shifted one-left bit and sign extended to 32 bits 10

11 THUMB Branch Instructions □Branch and link subroutine needs long-range, which is difficult within 16-bit range □THUMB uses two instructions to give a combined 22-bit half- word offset sign extended to 32 bits □The range of instruction is +/- 4 Mbytes. □Instructions are made independent by using interrupt and using link register as temporary memory. 11

12 THUMB Branch Instructions □‘oldPC’ -> address of second instruction □Return address has two bytes added to point to the next instruction □Bottom bit is set to indicate that the caller is a THUMB routine 12

13 THUMB Branch Instructions □Fourth format maps directly onto to the B {L} X instructions □r14 is set to the following instruction plus 1, indicating the caller was THUMB code. 13

14 Thumb Branch Assembler Formats □ Branch B ; format 1 – Thumb target B ; format 2 – Thumb target □ Branch with Link BL ; format 3 – Thumb target □ Branch with Link and eXchange BLX ; format 3a – ARM target B{L}X Rm ; format 4 – ARM or Thumb target 14

15 Conditional Branch 15

16 Conditional Branch □ Format 1 - Conditional Branch B ; example:.thumb Start: MOV R0, #50 MOV R1, #5 MOV R2, #20 …… Loop: SUB R0, R0, R1;subtract 5 from …… CMP R0, R2 BGE Loop;branch to loop if R0 is >= 20 16

17 Unconditional Branch □ Format 2 - Unconditional Branch B ; example:.thumb orange: …… B apple; branch to apple …… apple: …… B orange; branch to orange …… 17

18 Branch with Link □ Format 3 - Branch with link BL ; example:.thumb Loop: MOV R0, #50 MOV R1, #5 SUB R3, R0, R1 …… BL Surprise;branch to Surprise and save addr after branch …… Surprise: …… BX r14; return to instruction after branch.end 18

19 Branch with Link and Exchange □ Format 3a Only available in architecture v5T BLX ; example:.thumb …… BLX GREEN; branch to function GREEN …….arm …… GREEN: …… BX r14; Return to instruction after branch 19

20 Branch Exchange □ Format 4 - Branch Exchange with optional link B{L}X Rm ; example 1:example 2: (only architecture v5T).arm …… LDR r0, =RED+1 LDR r0, = BLUE+1 ;get addr of BLUE and MOV r14, pc ; save addr BLX r0 +1 to indicate Thumb BX r0in LR …… …….thumb.thumbBLUE: RED: …… …… BX lr BX r14 ; 20

21 THUMB Subroutines □ Theses branching formats allow us to have subroutine calls to functions in either instruction set □ How? B ; format 1 – Thumb target B ; format 2 – Thumb target BL ; format 3 – Thumb target BLX ; format 3a – ARM target B{L}X Rm ; format 4 – ARM or Thumb target 21

22 THUMB Subroutines 22

23 THUMB Data Processing Instructions 23

24 Data Processing Instructions □ Enable the programmer to perform arithmetic and logical operations on data values in registers □ Only instructions to modify data rather than move data around or control the sequence of program execution □ Typically require two operands and produce one result, but there are several exceptions (negate, move shifted register, etc.) 24

25 THUMB Data Processing Instructions □ More irregular formatting than standard ARM data processing instructions □ Most instructions set condition codes automatically, compared to standard ARM instructions which must explicitly be told to set condition codes □ Shift operations are separate from general ALU functions 25

26 Move Shifted Register 26

27 Move Shifted Register 27

28 ADD and SUBTRACT 28

29 Immediate Instructions 29

30 Logical/Additional Operations 30

31 Hi Register Operations 31

32 SP and PC Instructions 32

33 Conclusion 33

34 Overview □THUMB is a compressed, 16-bit subset of the ARM instruction set □Branching instructions used for loops, jumps, and subroutine calls □Data processing instructions allow for modification of data using arithmetic and logical procedures □Compressed THUMB instructions create a less consistent format 34

35 QUESTIONS 35

36 References □ (2015). “ARM Architecture.” Wikipedia. Web. February 14, □ Furber, S. (2000). ARM system-on-chip architecture. Harlow, England: Addison-Wesley. (2014). □ https://ece.uwaterloo.ca/~ece222/ARM/ARM7-TDMI-manual-pt3.pdf https://ece.uwaterloo.ca/~ece222/ARM/ARM7-TDMI-manual-pt3.pdf □ □ 36


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