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– 1 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 Successive Approximation (SA) ADC

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Successive Approximation ADC – 2 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 Binary search algorithm → N*T clk to complete N bits Conversion speed is limited by comparator, DAC, and digital logic (successive approximation register or SAR)

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Binary Search Algorithm – 3 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 DAC output gradually approaches the input voltage Comparator differential input gradually approaches zero

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Charge Redistribution SA ADC – 4 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall bit binary-weighted capacitor array DAC Capacitor array samples input when Φ 1 is asserted (bottom-plate)

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Charge Redistribution (MSB) – 5 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014

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Comparison (MSB) – 6 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 If V X V R /2, and MSB = 1, C 4 remains connected to V R If V X > 0, then V i < V R /2, and MSB = 0, C 4 is switched to ground

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Charge Redistribution (MSB-1) – 7 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014

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Comparison (MSB-1) – 8 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 If V X 3V R /4, and MSB-1 = 1, C 3 remains connected to V R If V X > 0, then V i < 3V R /4, and MSB-1 = 0, C 3 is switched to ground

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Charge Redistribution (Other Bits) – 9 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 Test completes when all four bits are determined w/ four charge redistributions and comparisons

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After Four Clock Cycles… – 10 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 Usually, half T clk is allocated for charge redistribution and half for comparison + digital logic V X always converges to 0 (V os if comparator has nonzero offset)

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Summing-Node Parasitics – 11 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 If V os = 0, C P has no effect eventually; otherwise, C P attenuates V X Auto-zeroing can be applied to the comparator to reduce offset

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Summary of SA ADC – 12 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall 2014 Power efficiency – only comparator consumes DC power DAC nonlinearity limits the INL and DNL of the SA ADC –N-bit precision requires N-bit matching from the cap array –Calibration can be performed to remove mismatch errors (Lee, JSSC’84) Comparator offset V os introduces an input-referred offset ~ (1+C P /ΣC j )*V os C P in general has little effect on the conversion (V X →0 at the end of the search); however, V X is always attenuated due to charge sharing of C P Binary search is sensitive to intermediate errors made during search – if an intermediate decision is wrong, the digitization process cannot recover –DAC must settle into ±½ LSB bound within the time allowed –Comparator offset must be constant (no hysteresis or time-dependent offset) –Non-binary search algorithm can be used (Kuttner, ISSCC’02)

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References – 13 – Data Converters Successive Approximation ADCProfessor Y. Chiu EECT 7327Fall J. L. McCreary and P. R. Gray, JSSC, pp , issue 6, R. E. Suarez, P. R. Gray, and D. A. Hodges, JSSC, pp , issue 6, H.-S. Lee, D. A. Hodges, and P. R. Gray, JSSC, pp , issue 6, M. de Wit, K.-S. Tan, and R. K. Hester, JSSC, pp , issue 4, C. M. Hammerschmied and H. Qiuting, JSSC, pp , issue 8, S. Mortezapour and E. K. F. Lee, JSSC, pp , issue 4, G. Promitzer, JSSC, pp , issue 7, F. Kuttner, ISSCC 2002, pp S. M. Chen and R. W. Brodersen, JSSC, pp , issue 2, N. Verma and A. Chandrakasan, ISSCC 2006, pp G. Van der Plas et al., ISSCC 2008, pp M. van Elzakker et al., ISSCC 2008, pp W. Liu, P. Huang, and Y. Chiu, JSSC, pp , issue 11, 2011.

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