Download presentation

Presentation is loading. Please wait.

1
**Successive Approximation (SA) ADC**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Successive Approximation (SA) ADC

2
**Successive Approximation ADC**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Successive Approximation ADC Binary search algorithm → N*Tclk to complete N bits Conversion speed is limited by comparator, DAC, and digital logic (successive approximation register or SAR)

3
**Binary Search Algorithm**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Binary Search Algorithm DAC output gradually approaches the input voltage Comparator differential input gradually approaches zero

4
**Charge Redistribution SA ADC**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Charge Redistribution SA ADC 4-bit binary-weighted capacitor array DAC Capacitor array samples input when Φ1 is asserted (bottom-plate)

5
**Charge Redistribution (MSB)**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Charge Redistribution (MSB)

6
**Data Converters Successive Approximation ADC Professor Y. Chiu**

EECT Fall 2014 Comparison (MSB) If VX < 0, then Vi > VR/2, and MSB = 1, C4 remains connected to VR If VX > 0, then Vi < VR/2, and MSB = 0, C4 is switched to ground

7
**Charge Redistribution (MSB-1)**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Charge Redistribution (MSB-1)

8
**Data Converters Successive Approximation ADC Professor Y. Chiu**

EECT Fall 2014 Comparison (MSB-1) If VX < 0, then Vi > 3VR/4, and MSB-1 = 1, C3 remains connected to VR If VX > 0, then Vi < 3VR/4, and MSB-1 = 0, C3 is switched to ground

9
**Charge Redistribution (Other Bits)**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Charge Redistribution (Other Bits) Test completes when all four bits are determined w/ four charge redistributions and comparisons

10
**After Four Clock Cycles…**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 After Four Clock Cycles… Usually, half Tclk is allocated for charge redistribution and half for comparison + digital logic VX always converges to 0 (Vos if comparator has nonzero offset)

11
**Summing-Node Parasitics**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Summing-Node Parasitics If Vos = 0, CP has no effect eventually; otherwise, CP attenuates VX Auto-zeroing can be applied to the comparator to reduce offset

12
**Summary of SA ADC Power efficiency – only comparator consumes DC power**

Data Converters Successive Approximation ADC Professor Y. Chiu EECT Fall 2014 Summary of SA ADC Power efficiency – only comparator consumes DC power DAC nonlinearity limits the INL and DNL of the SA ADC N-bit precision requires N-bit matching from the cap array Calibration can be performed to remove mismatch errors (Lee, JSSC’84) Comparator offset Vos introduces an input-referred offset ~ (1+CP/ΣCj)*Vos CP in general has little effect on the conversion (VX→0 at the end of the search); however, VX is always attenuated due to charge sharing of CP Binary search is sensitive to intermediate errors made during search – if an intermediate decision is wrong, the digitization process cannot recover DAC must settle into ±½ LSB bound within the time allowed Comparator offset must be constant (no hysteresis or time-dependent offset) Non-binary search algorithm can be used (Kuttner, ISSCC’02)

13
**Data Converters Successive Approximation ADC Professor Y. Chiu**

EECT Fall 2014 References J. L. McCreary and P. R. Gray, JSSC, pp , issue 6, 1975. R. E. Suarez, P. R. Gray, and D. A. Hodges, JSSC, pp , issue 6, 1975. H.-S. Lee, D. A. Hodges, and P. R. Gray, JSSC, pp , issue 6, 1984. M. de Wit, K.-S. Tan, and R. K. Hester, JSSC, pp , issue 4, 1993. C. M. Hammerschmied and H. Qiuting, JSSC, pp , issue 8, 1998. S. Mortezapour and E. K. F. Lee, JSSC, pp , issue 4, 2000. G. Promitzer, JSSC, pp , issue 7, 2001. F. Kuttner, ISSCC 2002, pp S. M. Chen and R. W. Brodersen, JSSC, pp , issue 2, 2006. N. Verma and A. Chandrakasan, ISSCC 2006, pp G. Van der Plas et al., ISSCC 2008, pp M. van Elzakker et al., ISSCC 2008, pp W. Liu, P. Huang, and Y. Chiu , JSSC, pp , issue 11, 2011.

Similar presentations

OK

ADC: Analog Digital Converters Successive Approximation Register (SAR)

ADC: Analog Digital Converters Successive Approximation Register (SAR)

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on competition commission of india Ppt on brand marketing company Ppt on touch screen technology download Ppt on types of web browser Download ppt on judiciary in india Ppt on transportation in plants Ppt on instrument landing system receiver Ppt on solar energy advantages and disadvantages Ppt on railway track clip Ppt on abo blood grouping