Presentation is loading. Please wait.

Presentation is loading. Please wait.

– 1 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Flash ADC.

Similar presentations


Presentation on theme: "– 1 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Flash ADC."— Presentation transcript:

1 – 1 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Flash ADC

2 Flash ADC Architecture – 2 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Reference ladder consists of 2 N equal size resistors Input is compared to 2 N -1 reference voltages Massive parallelism Very fast ADC architecture Throughput = f s Latency = 1 T = 1/f s Complexity = 2 N

3 Thermometer Code – 3 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Thermometer code 1-of-n code

4 Flash ADC Challenges – 4 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 V DD = 1.8 V 10-bit V FS = 1 V DNL < 0.5 LSB 0.5 mV = 3-5 σ →1023 comparators →1 LSB = 1 mV →V os < 0.5 LSB →σ = mV 2 N -1 very large comparators Large area, large power consumption Very sensitive design Limited to resolutions of 4-8 bits

5 Flash ADC Challenges – 5 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 DNL < 0.5 LSB Large V FS relaxes offset tolerance Small V FS benefits conversion speed (settling, linearity of building blocks)

6 A Typical CMOS Comparator – 6 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 V os derives from: Preamp input pair mismatch (V th,W,L) PMOS loads and current mirror Latch mismatch CI / CF imbalance of M 9 Clock routing Parasitics

7 Latch Regeneration – 7 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Exponential regeneration due to positive feedback of M 7 and M 8

8 Regeneration Speed – Linear Model – 8 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 

9 Reg. Speed – Linear Model – 9 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 VoVo V o (t=0)t/(C L /g m ) 1V100mV2.3 1V10mV4.6 1V1mV6.9 1V100μV9.2

10 Reg. Speed – Linear Model – 10 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014  x

11 Comparator Metastability – 11 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Comparator fails to produce valid logic outputs within T/2 when input falls into a region that is sufficiently close to the comparator threshold CurveA V1 A V2 V i (t=0)  mV  10 1 mV μV  μV

12 Comparator Metastability – 12 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Cascade preamp stages (typical flash comparator has 2-3 PA stages) Use pipelined multi-stage latches; PA can be pipelined too Avoid branching off comparator logic outputs Assuming that the input is uniformly distributed over V FS, then

13 Comparator Metastability – 13 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Logic levels can be misinterpreted by digital gates (branching off, diff. outputs) – even a wrong decision is better than no decision!

14 CI and CF in Latch – 14 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Charge injection and clock feedthrough introduce CM jump in V o + and V o - Dynamic latches are more susceptible to CI and CF errors

15 Dynamic Offset of Latch – 15 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Dynamic offset derives from: Imbalanced CI and CF Imbalanced load capacitance Mismatch b/t M 7 and M 8 Mismatch b/t M 5 and M 6 Clock routing Dynamic offset is usually the dominant offset error in latches

16 Typical CMOS Comparator – 16 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Input-referred latch offset gets divided by the gain of PA Preamp introduces its own offset (mostly static due to V th, W, and L mismatches) PA also reduces kickback noise Kickback noise disturbs reference voltages, must settle before next sample

17 Comparator Offset – 17 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Differential pair mismatch: Total input-referred comparator offset:

18 Matching Properties – 18 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Suppose parameter P of two rectangular devices has a mismatch error of ΔP. The variance of parameter ΔP b/t the two devices is where, W and L are the effective width and length, D is the distance Ref: M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, pp , issue 5, st term dominates for small devices

19 Why Large Devices Match Better? – 19 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 R1R1 R2R2 “Spatial averaging”

20 ADC Input Capacitance – 20 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 N = 6 bits V FS = 1 V σ = LSB/4 A VT0 = 10 mV·μm →63 comparators →1 LSB = 16 mV →σ = 4 mV →L = 0.24 μm, W = 26 μm N (bits)# of comp.C in (pF) ??! Small V os leads to large device sizes, hence large area and power Large comparator leads to large input capacitance, difficult to drive and difficult to maintain tracking bandwidth

21 – 21 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Flash ADC Errors

22 Distributed Parallel Processing – 22 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 SHA-less Signal and clock propa- gation delay 2 N -1 PAs + latches must be matched Synchronized strobe signal is critical Going parallel is fast, but also gives rise to inherent problems…

23 Preamp Input Common Mode – 23 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Input CM difference creates systematic mismatch (offset, gain, C in, tracking BW, and CMRR) among preamps

24 Sampling Aperture Error – 24 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Preamp delay and V th of sampling switch (M 9 ) are both signal-dependent → signal-dependent sampling point (aperture error) A major challenge of distributing clock signals across 2 N -1 comparators in flash ADC with minimum clock skew (routing, V th mismatch of M 9, etc.) ΦMode “high”Track “low”Regen

25 Nonlinear Input Capacitance – 25 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Signal-dependent input bandwidth (1/R S C in ) introduces distortion

26 Input Signal Feedthrough – 26 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Feedthrough of V in to the reference ladder through the serial connection of C gs1 and C gs2 disturbs the reference voltages

27 Fully-Differential Architecture – 27 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 V FS doubled 3-dB gain in SNR Better CMRR Noise immunity Input feedthrough cancelled C in nonlinearity partially removed Effect of V cmi diff. mitigated

28 Fully-Differential Comparator – 28 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Double-balanced, fully-differential preamp Switches (M 7, M 8 ) added to stop input propagation during regeneration Active pull-up PMOS added to the latch

29 AC-Coupled Preamp – 29 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 PA input node X sees constant bias throughout all preamps Autozeroing eliminates PA offsets (stored in C) Ref: A. G. F. Dingwall, “Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter,” IEEE Journal of Solid-State Circuits, vol. 14, pp , issue 6, 1979.

30 Bubbles (Sparkles) – 30 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Static/dynamic comparator errors cause bubbles in thermometer code

31 Bubbles (Sparkles) – 31 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Comparator offsetTiming error

32 Bubble-Tolerant Boundary Detector – 32 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Ref: J. G. Peterson, “A monolithic video A/D converter,” IEEE Journal of Solid-State Circuits, vol. 14, pp , issue 6, input NAND Detect “011” instead of “01” only “Single” bubble correction Biased correction

33 Built-In Bias – 33 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Case “011” Det. “001” Det. A  BFail  C  D Inspecting more neighboring comparator outputs improves performance

34 Majority Voting – 34 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Ref: C. W. Mangelsdorf, “A 400-MHz input flash converter with error correction,” IEEE Journal of Solid-State Circuits, vol. 25, pp , issue 1, Case “011” Det. Majority voting A  BFail  C  D

35 Gray Encoding – 35 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 One comparator output is ONLY used once → No branching! Gray encoding fails benignly in the presence of bubbles Codes are also robust over metastability errors Only one transition b/t adjacent codes

36 Gray Encoding – 36 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Conversion of Gray code to binary code is quite time-consuming → “quasi” Gray code Ref: Y. Akazawa, et al., “A 400MSPS 8b flash AD conversion LSI,” in IEEE International Solid-State Circuits Conference, Dig. Tech. Papers, 1987, pp


Download ppt "– 1 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Flash ADC."

Similar presentations


Ads by Google