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– 1 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 CMOS Comparator.

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Presentation on theme: "– 1 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 CMOS Comparator."— Presentation transcript:

1 – 1 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 CMOS Comparator

2 Comparator – 2 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Transfer characteristic (ideal) Circuit symbol Detects the polarity of the analog input signal and produces a digital output (1 or 0) accordingly – threshold-crossing detector

3 Applications – 3 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Voltage/current level comparison (A/D conversion) Digital communication receivers (“slicer” or decision circuit) Sense amplifier in memory readout circuits Power electronics with digital control (dc-dc converter)

4 Design Considerations – 4 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Accuracy (offset, noise, resolution) Settling time (tracking BW, regeneration speed) Sensitivity (gain) Metastability (any decision is better than no decision!) Overdrive recovery (memory) CMRR Power consumption

5 Comparator – 5 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 AmplificationClipping Precise gain and linearity are often unnecessary → simple, low-gain, open- loop, wideband amplifiers + latch (positive feedback) More gain can be derived by cascading multiple gain stages Built-in sampling function with latched comparators 

6 Multi-Stage Preamp – 6 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 N stages:

7 Step Response – 7 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014

8 Optimum N – 8 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Given A 0 = V o /V i, N opt can be determined with the above equation For A 0 < 100, typical N value ranges between 2 and 4

9 Comparison – 9 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 A higher A 0 (= V o /V i ) requires a larger N In comparison, latches regenerate faster than preamps

10 Multi-Stage PA Offset – 10 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Total input-referred Individual stage 

11 Input Offset Cancellation – 11 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 AC coupling at input with input-referred offset stored in C Two-phase operation, one phase (Φ 2 ) is used to store offset

12 Offset Storage – Φ 2 – 12 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014  Closed-loop stability (amplifier in unity-gain feedback) Ref: J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques. I,” JSSC, vol. 10, pp , issue 6, 1975.

13 Amplifying Phase – Φ 1 – 13 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014  Offset cancellation is incomplete if A is finite Input AC coupling attenuates signal gain

14 CF and CI of Switches – 14 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 What’s the optimum phase relationship between Φ 2 and Φ 2 '? Bottom-plate sampling → Φ 2 ' switches off slightly before Φ 2 (note the operation in this phase is signal independent anyway)

15 Output Offset Cancellation – 15 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 AC coupling at output with offset stored in C A must be small and well controlled (independent of V o ) Does not work for high-gain op-amps

16 Offset Storage – Φ 2 – 16 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014  Closed-loop stability is not required CF and CI of Φ 2 ' gets divided by A when referred to input Ref: R. Poujois and J. Borel, “A low drift fully integrated MOSFET operational amplifier,” JSSC, vol. 13, pp , issue 4, 1978.

17 Amplifying Phase – Φ 1 – 17 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014  Cancellation is complete if A is constant (independent of V o ) AC coupling at output attenuates signal gain

18 Offset Cancellation w/ Auxiliary Input – 18 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 G m1 and G m2 are the preamp and latch, respectively A form of output offset cancellation technique Ref: B. Razavi and B. A. Wooley, “Design techniques for high-speed, high-resolution comparators,” JSSC, vol. 27, pp , issue 12, 1992.

19 Offset Sampling – 19 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 G m1 and G m2 are grounded and the PFB of G m2 is disabled V os1 and V os2 are amplified by G m1 and G m2 to appear at V o When S 5 & S 6 open (slightly before S 3 & S 4 ), offset voltage is sampled and stored in C 1 and C 2 CF/CI of S 5 & S 6 gets divided by (G m1 /G m2 ) when referred to input S 3 -S 6 closed S 1 -S 2 open

20 Comparison – 20 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Differential input is amplified by G m1 to establish an imbalance at the output and AC coupled to the input of G m2 G m2 starts regeneration with this imbalance S 3 -S 6 open S 1 -S 2 closed

21 Potential Problems – 21 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Very complicated → slow conversion speed C 1 and C 2 and their parasitics add loading to the output Finite on-resistance of S 5 & S 6 cannot completely break PFB CF/CI imbalance of S 5 & S 6 can trigger regeneration

22 Razavi’s Comparator – 22 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Even more complicated!

23 – 23 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Overdrive Recovery

24 Overdrive Recovery Test – 24 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 A small input (±0.5 LSB) is applied to the comparator input in a cycle right after a full-scale input is applied; the comparator should be able to resolve to the right output in either case → memoryless “0”“1” Case ICase II

25 Passive Clamp – 25 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Limit the output swing with diode clamps → signal-dependent R o Clamps add parasitics to the PA output

26 Active Reset – 26 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Kill PA gain with a crowbar switch → time-dependent R o Switch adds parasitics to the PA output

27 PA Autozeroing – 27 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Two-phase operation, Φ 2 phase is used for offset storage Autozeroing switch Φ 2 ' also resets and removes the PA memory

28 – 28 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 CMOS Preamplifier

29 Pull-Up – 29 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 NMOS pull-up suffers from body effect, affecting gain accuracy PMOS pull-up is free from body effect, but subject to P/N mismatch Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion, well, etc.) don’t track transistors; but it is fast!

30 To Obtain More Gain – 30 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 I p diverts current away from PMOS diodes (M 3 & M 4 ), reducing (W/L) 3 Higher gain w/o CMFB Needs biasing for I p M 3 & M 4 may cut off for large V in, resulting in a slow recovery

31 Bult’s Preamp – 31 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 NMOS diff. pair loaded with PMOS diodes and PMOS latch (PFB) High DM gain, low CM gain, good CMRR Simple, no CMFB (W/L) 34 > (W/L) 56 needs to be ensured for stability Ref: K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm 2,” JSSC, vol. 32, pp , issue 12, 1997.

32 DM – 32 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 

33 CM – 33 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 

34 Song’s Preamp – 34 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 NMOS diff. pair loaded with PMOS diodes and resistors High DM gain, low CM gain, good CMRR Simple, no CMFB Gain not well-defined Ref: B.-S. Song et al., “A 1 V 6 b 50 MHz current-interpolating CMOS ADC,” in Symp. VLSI Circuits, 1999, pp

35 Song’s Preamp – 35 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 DMCM

36 – 36 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 CMOS Latch

37 Static Latch – 37 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Active pull-up and pull- down → full CMOS logic levels Very fast! Q + and Q - are not well defined in reset mode (Φ = 1) Large short-circuit current in reset mode Zero DC current after full regeneration Very noisy

38 Semi-Dynamic Latch – 38 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Diode divider disabled in reset mode → less short-circuit current Pull-up not as fast Q + and Q - are still not well defined in reset mode (Φ = 1) Zero DC current after full regeneration Still very noisy

39 Current-Steering Latch – 39 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Constant current → very quite Higher gain in tracking mode Cannot produce full logic levels Fast Trip point of the inverters

40 Dynamic Latch – 40 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Zero DC current in reset mode Q + and Q - are both reset to “0” Full logic level after regeneration Slow No seed voltage Ref: A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC, vol. 20, pp , issue 3, 1985.

41 Modified Dynamic Latch – 41 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 Ref: T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” JSSC, vol. 30, pp , issue 3, Zero DC current in reset mode Q + and Q - are both reset to “0” Full logic level after regeneration Slow No seed voltage

42 Cho’s Comparator – 42 – Data ConvertersComparatorProfessor Y. Chiu EECT 7327Fall 2014 M 1R and M 2R added to set the comparator threshold 


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