Download presentation

Presentation is loading. Please wait.

0
**Princess Sumaya University**

Digital Logic Design Digital Logic Design Chapter 6: Registers and Counters Dr. Bassam Kahhaleh

1
**Princess Sumaya University**

Digital Logic Design Registers Group of D Flip-Flops Synchronized (Single Clock) Store Data D Q R Reset CLK I0 I1 I2 I3 A0 A1 A2 A3 Dr. Bassam Kahhaleh

2
**Note: New data has to go in with every clock**

Registers CLK D Q R Reset CLK I0 I1 I2 I3 A0 A1 A2 A3 I3 I2 I1 I0 A3 A2 A1 A0 Note: New data has to go in with every clock

3
**Registers with Parallel Load**

Control Loading the Register with New Data R E G I S T E R D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD LD Q(t+1) Q(t) 1 D

4
**Registers with Parallel Load**

Should we block the “Clock” to keep the “Data”? R E G I S T E R D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD D Q CLK I0 A0 I1 A1 I2 A2 I3 A3 Load Delays the Clock

5
**Registers with Parallel Load**

Circulate the “old data” MUX I0 I1 Y S D Q A0 I0 MUX I0 I1 Y S D Q A1 I1 MUX I0 I1 Y S D Q A2 I2 MUX I0 I1 Y S D Q A3 I3 Load CLK

6
**Shift Registers 4-Bit Shift Register Serial Input D Q CLK SI SO**

Serial Output

7
**Shift Registers Q3 Q2 Q1 Q0 D Q D Q D Q D Q SI SO CLK CLK SI Q3 Q2 Q1**

8
**Serial Transfer SI SO SI Shift Register A Shift Register B CLK CLK**

Clock Shift Control Clock Shift Control CLK

9
**Serial Addition Shift Control SI Shift Register A FA x y z S C**

Shift Register B CLK Q D CLR Clear

10
**Universal Shift Register**

Parallel-in Parallel-out Serial-in Serial-out Serial-in Parallel-out Parallel-in Serial-out D Q D Q D Q D Q

11
**Universal Shift Register**

Q3 Q2 Q1 Q0 D Q CLR CLK S1 S0 MUX I3 I2 I1 I0 Y S1 S0 SI for SR SI for SL D3 D2 D1 D0

12
**Universal Shift Register**

Q3 Q2 Q1 Q0 S1 CLR S0 USR SRin SLin D3 D2 D1 D0 Mode Control Register Operation S1 S0 No change 1 Shift right Shift left Parallel load

13
**Ripple Counters Ripple ↔ Asynchronous T Q CLR Q3 Q2 Q1 Q0 CLK 1 CLK Q0**

14
**Ripple Counters Q3 Q2 Q1 Q0 D Q D Q D Q D Q CLK CLK Q0 Q1 Q2 Q3 1 2 3**

1 2 3 4 5 6 7 8 9

15
**BCD Ripple Counter J Q K CLK 1 Q3 Q2 Q1 Q0 0000 0001 0010 0011 0100**

1001 1000 0111 0110 0101 J Q K CLK 1 Q3 Q2 Q1 Q0

16
**Decades Counter Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 BCD Counter**

(CLK) 100’s Digit 10’s Digit 1’s Digit

17
**Synchronous Binary Counter**

Q3 Q2 Q1 Q0 Enable J Q K J Q K J Q K J Q K To Next Stage CLK

18
**Up-Down Binary Counter**

Q3 Q2 Q1 Q0 T Q T Q T Q T Q CLK Up Down

19
BCD Counter 1 1 1 1 0000 0001 0010 0011 0100 1 1 1001 1000 0111 0110 0101 1 1 1 1 Q3 Q2 Q1 Q0 E

20
BCD Counter 1 1 1 1 0000 / 0 0001 / 0 0010 / 0 0011 / 0 0100 / 0 1 1 1001 / 1 1000 / 0 0111 / 0 0110 / 0 0101 / 0 1 1 1 1 Q3 Q2 Q1 Q0 y E

21
**Binary Counter with Parallel Load**

Q3 CLR LD Count Q(t+1) x 1 Q(t) Q(t)+1 I I2 Q2 I1 Q1 I0 Q0 LD Count CLR Usually Asynchronous Clear

22
**BCD Counter Example LD I3 Q3 A3 I2 Q2 A2 I1 Q1 A1 I0 Q0 A0 Count Count**

I3 Q3 A3 I2 Q2 A2 I1 Q1 A1 I0 Q0 A0 Count Count CLR 1 CLK

23
**Ring Counter 2-bit counter 2-to-4 Decoder T3 T2 T1 T0 CLK T0 T1 T2 T3**

0001 0010 0100 1000 2-bit counter 2-to-4 Decoder T3 T2 T1 T0 CLK T0 T1 T2 T3

24
**Johnson Counter D Q CLK Q3 Q2 Q1 Q0 0000 0001 0011 0111 1000 1100 1110**

1111 D Q CLK Q3 Q2 Q1 Q0

25
Homework Mano Chapter 6 6-2 6-3 6-4 6-13 6-14 6-16 6-18

26
Homework 6-2 Include a synchronous clear input to the “Register with Parallel Load”. The modified register will have a parallel load capability and a synchronous clear capability. The register is cleared synchronously when the clock goes through a positive transition and the clear input is equal to 1. 6-3 What is the difference between serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial. What type of register is needed?

27
Homework 6-4 The content of a 4-bit register is initially The register is shifted six times to the right with the serial input being What is the content of the register after each shift? 6-13 Show that a BCD ripple counter can be constructed using a 4-bit binary ripple counter with asynchronous clear and a NAND gate that detects the occurrence of count 1010. 6-14 How many flip-flop will be complemented in a 10-bit binary ripple counter to reach the next count after the following count: (a) (b) (c)

28
Homework 6-16 The BCD ripple counter has four flip-flops and 16 states, of which only 10 are used. Analyze the circuit and determine the next state for each of the other six unused states. What will happen if a noise signal sends the circuit to one of the unused states? 6-18 What operation is performed in the up-down counter when both the up and down inputs are enabled? Modify the circuit so that when both inputs are equal to 1, the counter does not change state, but remains in the same count.

Similar presentations

Presentation is loading. Please wait....

OK

Registers & Counters M. Önder Efe

Registers & Counters M. Önder Efe

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on historical places in india free download Ppt on types of chromosomes Ppt on pirates of silicon valley Ppt on environmental issues in india Ppt on limits and derivatives tutorial Ppt on nitrogen cycle and nitrogen fixation cycle Ppt on endangered species of india and africa Ppt on water scarcity in south Ppt on unemployment in india download Educational backgrounds for ppt on social media