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Chapter 6:. 1 / 28 Registers  Group of D Flip-Flops  Synchronized (Single Clock)  Store Data DQ R Reset DQ R DQ R DQ R CLK I0I0 I1I1 I2I2 I3I3 A0A0.

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Presentation on theme: "Chapter 6:. 1 / 28 Registers  Group of D Flip-Flops  Synchronized (Single Clock)  Store Data DQ R Reset DQ R DQ R DQ R CLK I0I0 I1I1 I2I2 I3I3 A0A0."— Presentation transcript:

1 Chapter 6:

2 1 / 28 Registers  Group of D Flip-Flops  Synchronized (Single Clock)  Store Data DQ R Reset DQ R DQ R DQ R CLK I0I0 I1I1 I2I2 I3I3 A0A0 A1A1 A2A2 A3A3

3 2 / 28 Registers DQ R Reset DQ R DQ R DQ R CLK I0I0 I1I1 I2I2 I3I3 A0A0 A1A1 A2A2 A3A3 I3I3 I2I2 I1I1 I0I0 A3A3 A2A2 A1A1 A0A0 Note Note: New data has to go in with every clock

4 3 / 28 Registers with Parallel Load Loading  Control Loading the Register with New Data REGISTERREGISTER D7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0 Q7Q6 Q5Q4Q3Q2 Q1Q0Q7Q6 Q5Q4Q3Q2 Q1Q0 LD Q(t+1) 0Q(t)Q(t) 1D

5 4 / 28 Registers with Parallel Load  Should we block the “Clock” to keep the “Data”? DQ CLK I0I0 A0A0 DQ I1I1 A1A1 DQ I2I2 A2A2 DQ I3I3 A3A3 Load Delays the Clock REGISTERREGISTER D7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0 Q7Q6 Q5Q4Q3Q2 Q1Q0Q7Q6 Q5Q4Q3Q2 Q1Q0 LD

6 5 / 28 Registers with Parallel Load  Circulate the “old data” DQ CLK I0I0 A0A0 DQ I1I1 A1A1 DQ I2I2 A2A2 DQ I3I3 A3A3 Load MUX I0I1I0I1 Y S I0I1I0I1 Y S I0I1I0I1 Y S I0I1I0I1 Y S

7 6 / 28 Shift Registers  4-Bit Shift Register Serial Input Serial Output DQDQDQDQ CLK SISO

8 7 / 28 Shift Registers DQDQDQDQ CLK SI SO Q3Q3 SI Q2Q2 Q1Q1 Q0Q0 CLK Q3Q3 Q2Q2 Q1Q1 Q0Q0

9 8 / 28 Serial Transfer Shift Register A SI Shift Register B SOSI Clock Shift Control CLK Clock CLK

10 9 / 28 Serial Addition FA Shift Register A xyzxyz SCSC QD CLR CLK Shift Control Clear Shift Register B SI

11 10 / 28 Universal Shift Register  Parallel-in Parallel-out  Serial-in Serial-out  Serial-in Parallel-out  Parallel-in Serial-out DQDQDQDQ

12 11 / 28 Universal Shift Register D Q D Q D Q D Q MUX I 3 I 2 I 1 I 0 Y S1S0S1S0 Q3Q3 Q2Q2 Q1Q1 Q0Q0 D1D1 S1S0S1S0 CLK CLR D0D0 D2D2 D3D3 SI for SR SI for SL

13 12 / 28 Universal Shift Register Q3Q3 Q2Q2 Q1Q1 Q0Q0 D3D3 D2D2 D1D1 D0D0 S1S1 S0S0 USR CLR SR in SL in Mode Control Register Operation S1S1 S0S0 00No change 01Shift right 10Shift left 11Parallel load

14 13 / 28 Ripple Counters  Ripple ↔ Asynchronous TQ CLR TQ TQ TQ Q3Q3 Q2Q2 Q1Q1 Q0Q0 CLK CLR 1111 CLK Q0Q0 Q1Q1 Q2Q2 Q3Q3

15 14 / 28 Ripple Counters DQ Q DQ Q DQ Q DQ Q Q3Q3 Q2Q2 Q1Q1 Q0Q0 CLK Q0Q0 Q1Q1 Q2Q2 Q3Q3 0123456789

16 15 / 28 BCD Ripple Counter 00000001 001000110100 10011000 0111 0110 01010101 JQ Q K CLK 1 1 JQ Q K 1 JQ Q K 1 1 JQ Q K 1 Q3Q3 Q2Q2 Q1Q1 Q0Q0

17 16 / 28 Decades Counter BCD Counter Q3Q3 Q2Q2 Q1Q1 Q0Q0 Q3Q3 Q2Q2 Q1Q1 Q0Q0 Q3Q3 Q2Q2 Q1Q1 Q0Q0 Count 1’s Digit 10’s Digit 100’s Digit (CLK)

18 17 / 28 Synchronous Binary Counter JQ Q K CLK Enable Q3Q3 Q2Q2 Q1Q1 Q0Q0 JQ Q K JQ Q K JQ Q K To Next Stage

19 18 / 28 Up-Down Binary Counter TQ Q Up TQ Q TQ Q TQ Q Q3Q3 Q2Q2 Q1Q1 Q0Q0 Down CLK

20 19 / 28 BCD Counter 00000001001000110100 100110000111011001010101 Q3Q3 Q2Q2 Q1Q1 Q0Q0 E 00000 00000 1111 1111 1 1

21 20 / 28 BCD Counter 0000 / 00001 / 00010 / 00011 / 00100 / 0 1001 / 11000 / 00111 / 00110 / 00101 / 0 Q3Q3 Q2Q2 Q1Q1 Q0Q0 yE 00000 00000 1111 1111 1 1

22 21 / 28 Binary Counter with Parallel Load Q3Q3 Q2Q2 Q1Q1 Q0Q0 LD I3I3 I2I2 I1I1 I0I0 Count CLRLDCountQ(t+1) 0xx0 100Q(t)Q(t) 101Q(t)+1 11xI CLR Usually Asynchronous Clear

23 22 / 28 BCD Counter Example Q3Q3 Q2Q2 Q1Q1 Q0Q0 LD I3I3 I2I2 I1I1 I0I0 Count CLR 0 0 0 0 A3A3 A2A2 A1A1 A0A0 1 CLK Count

24 23 / 28 Ring Counter 1000000100100100 2-bit counter 2-to-4 Decoder T3T3 T2T2 T1T1 T0T0 CLK T0T0 T1T1 T2T2 T3T3

25 24 / 28 Johnson Counter 0111000000010011 1111100011001110 DQ Q CLK DQ Q DQ Q DQ Q Q3Q3 Q2Q2 Q1Q1 Q0Q0

26 25 / 28 Homework  Mano ●Chapter 6 ♦ 6-2 ♦ 6-3 ♦ 6-4 ♦ 6-13 ♦ 6-14 ♦ 6-16 ♦ 6-18

27 26 / 28 Homework 6-2Include a synchronous clear input to the “Register with Parallel Load”. The modified register will have a parallel load capability and a synchronous clear capability. The register is cleared synchronously when the clock goes through a positive transition and the clear input is equal to 1. 6-3What is the difference between serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial. What type of register is needed?

28 27 / 28 Homework 6-4The content of a 4-bit register is initially 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of the register after each shift? 6-13Show that a BCD ripple counter can be constructed using a 4-bit binary ripple counter with asynchronous clear and a NAND gate that detects the occurrence of count 1010. 6-14How many flip-flop will be complemented in a 10-bit binary ripple counter to reach the next count after the following count: (a) 1001100111 (b) 0011111111 (c) 1111111111

29 28 / 28 Homework 6-16The BCD ripple counter has four flip-flops and 16 states, of which only 10 are used. Analyze the circuit and determine the next state for each of the other six unused states. What will happen if a noise signal sends the circuit to one of the unused states? 6-18What operation is performed in the up-down counter when both the up and down inputs are enabled? Modify the circuit so that when both inputs are equal to 1, the counter does not change state, but remains in the same count.


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