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Lab 11 : Memory System Fundamentals : Slide #2 Slide #3 Slide #4 Slide #5 ROM Light Sequencer : RAM Fundamentals : ROM Fundamentals : ROM application :

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Presentation on theme: "Lab 11 : Memory System Fundamentals : Slide #2 Slide #3 Slide #4 Slide #5 ROM Light Sequencer : RAM Fundamentals : ROM Fundamentals : ROM application :"— Presentation transcript:

1 Lab 11 : Memory System Fundamentals : Slide #2 Slide #3 Slide #4 Slide #5 ROM Light Sequencer : RAM Fundamentals : ROM Fundamentals : ROM application : Slide #6 4X4 Bidirectional I/O RAM:

2 Here is what happens if address = 1,0 Here is what happens if address = 0,1 IF address = 0,0 then output 0 of the decoder will be asserted. The top tri-state buffer is asserted. The data bus will come out of HiZ and output the contents of the Q0 memory cell. The Address Bus pins determine which decoder output that gets asserted. The CS pin will be connected to GND. This will enable the decoder and make one of the decoder outputs active (logic 0). CS is the Enable input of 1 of 4 decoder. CS= 1 disables decoder. All outputs (O0, O1, O2, O3) =1. The CS (Chip Select) input makes up the Control Bus. For CS=0 the chip is selected and memory can be accessed. For CS=1 the memory cannot be accessed and the Data Bus = HiZ. The content of the memory cell is accessed via the Data Bus pin. The equation used to describe the storage capacity of the ROM is 4X1 ( four 1 bit memory cells). Each cell is a transistor with a programmable fuse. To store a 1 leave the fuse intact. To store 0 burn out the fuse. Lab 11: ROM Fundamentals : The internal construction of a 4 Bit ROM can be used to introduce ROM fundamental concepts. Fuse intact = Transistor Saturation 1 Burnt fuse = Transistor Cut-off. 0 Data Bus Control Bus =E Logic 1 at the enable input of the tri-state buffer will make the Data Bus HiZ (open circuit/no signal) Tri-State Buffer with active low enable. Thus HiZ out! Address Bus 0 Data Bus = Cell Q Data Bus = Cell Q Data Bus = Cell Q2 1 0 Here is what happens if address = 1, Data Bus = Cell Q3 As you can see the Address Bus controls which memory cell sends its data to the Data Bus. Each memory cell has its own address just like each house on a street is identified with an address. The house address identifies the occupants (data). The memory address identifies the binary data in a memory cell. The Control Bus can shut down the Data Bus. The Data Bus can be put into HiZ if the CS=1. Slide #2

3 Many years ago a PAY TV de-scrambler system was nothing more than a computer that read (accessed) the content of a ROM to see what channels would be de-scrambled. Lab 11 : ROM Pay TV System Application : ROM memory ICs must first be programmed before they can be used in a computer system. To illustrate this, lets assume the 4 bit ROM is used in a 1 st generation PAY TV de-scrambler system. Lets assume the de-scrambler allows a customer to choose among 4 PAY TV channels. Lets assume the customer requests a de-scrambler that can de-scramble only the first 2 channels. The cable company would receive a call from the customer and would program the ROM. A blank ROM would be inserted into a programming station and the bottom 2 fuses would be burnt The ROM would be inserted into the PAY TV de-scrambler computer system and given to the customer. The customer would attach the system to their TV. On power up the computer would need to cycle the address bus inputs while reading the data bus to see which channels need de- scrambling. 0 Yes De-scramble Yes de-scramble! Do not de-scramble A ROM must be programmed before it can be used in a system. The contents of ROM are read (accessed) sequentially (one cell after the other) by the computer system. Slide #3

4 Lab 11 : 16X8 ROM Light Sequencer: We will use a 16X8 ROM to create a light sequencing system. This application will also introduce the concept of a Memory Map Diagram. D0 A0 A3 A1 A2 D1 D2 D3 D4 D5 D6 D7CS 16X8 ROM A 16X8 ROM can store 16 different 8 bit data codes. To store 16 codes the ROM requires 4 address inputs (2 4 =16). The data stored in the ROM will be read (transferred) to 8 LEDs. Note: Logic 1 = LED on … Logic 0 = LED off. The address inputs will be cycled by a mod 16 counter. Q1 Q0 Q2 Q3 >clk Data Bus Add. Bus A Memory Map Diagram is a table that shows the content of a programmed ROM. A blank ROM has all data at 0. Here is the Memory Map Diagram of a blank ROM. The user of a ROM decides what data codes are needed for the application and generates a Memory Map Diagram. The diagram is used to program the IC. Here is the diagram for the Light Sequencer. Attach a 1 PPS clock to the input of the counter and this is what you will see on the LEDs. Use the backspace key to replay the animation Data Bus Add. Bus To change the light sequence pattern all you need to do is erase the ROM, create a new Memory Map Diagram, re-program the ROM and re-insert it into the system. This type of change is much simpler than a complete re-design of an entire logic system. Slide #4

5 An SRAM is used to write data and to later read it back. Lets assume the SRAM has all 64 data codes are 0,0,0, Write Operation Example: Write the number 9 into register 2. Step 1: Apply signals to the Address Bus. Register 2 = Address Step 2: Apply signals to the Data Bus. Data =9 = Step 3: Apply signals to the Control Bus. R/W =0 to write … CS=0 to enable IC. This will enable the Input Buffers. Output Buffers stay in HiZ (no contention) In the write mode all pins on the SRAM must be driven. All pins are inputs Read Operation Example: Read the number 9 from register 2. Step 1: Apply signals to the Address Bus. Register 2 = Address Step 2: Make sure you are no longer driving the Data Bus pins. Reading means the data bus will output the number 9. Connect LEDs to data bus if you would like to display the number. Step 3: Apply signals to the Control Bus. R/W =1 to read … CS=0 to enable IC. This will enable the Output Buffers. Input Buffers are in HiZ In the read mode the Address and Control Bus pins must be driven. The Data Bus pins are outputs and must NOT be driven. Driving the Data Bus pins could result in damage to the IC. Lab 11 : RAM Fundamentals: A 64X4 SRAM is a Static RAM. It has 6 address pins (2 6 =64). Static implies that the memory cells, in each 4 bit register, are flip flops. It has bidirectional I/O pins. Slide #5

6 Lab 11 : 4X4 Bidirectional I/O RAM: Most digital systems use separate operations to read and write RAM. The RAM never needs to be read from or written to at the same time. For this reason there is no need to provide separate D inputs and Q outputs. Combining D and Q reduces the number of inputs and outputs. It creates a bidirectional I/O RAM. Slide #6 The write enable control input can be used to control the flow of data into or out of the memory device. WE = 1 for write operations and WE = 0 for read operations. When WE = 1 the Output Buffers are in HiZ and the D/Q lines can safely write data into the registers without bus contention. An active voltage source (like a switch) is required to drive the D/Q lines. 0 HiZ Write to memory When WE = 0 the Output Buffers will allow data to be read from the registers. Data is output from the registers to the D/Q lines. The active voltage source, which was used to write data into memory, must be removed in order to prevent bus contention. A passive device like an LED can be used to view the contents of memory. 1 Read Memory OE is called output enable.OE can be used to enable theOutput Buffers to be used to write and read data. OE can also be used to completely disable theOutput Buffers and keep theD/Q lines continuously in HiZ. When OE = 1 the Output Buffers are enabled and are in turn controlled by WE. 1/0 Write and Read 11/0 0/1 When OE = 0 the Output Buffers are NOT enabled and can no longer be controlled by WE. They remain continuously in HiZ regardless of the condition at WE. 0 HiZ X 1 1 WE no longer controls theOutput Buffers 0 CS is called chip select. UnlikeOE which only controls the status of the Output Buffers, CS can be used to enable or totally disable the entire RAM semiconductor (chip). When CS = 1, the 1 of 4 decoder is enabled and the RAM operates normally. Write and read operations can be performed. When CS = 0, the 1 of 4 decoder is disabled and all decoder outputs are 0. With the decoder outputs at 0, all internal registers (R0, R1, R2, R3) will have their local buffers in HiZ and their Ena inputs disabled. This totally shuts down any write and read operations. 0 HiZ X X X X


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