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Chapter 4:. 1 / 65 Combinational Circuits  Output is function of input only i.e. no feedback When input changes, output may change (after a delay) n.

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Presentation on theme: "Chapter 4:. 1 / 65 Combinational Circuits  Output is function of input only i.e. no feedback When input changes, output may change (after a delay) n."— Presentation transcript:

1 Chapter 4:

2 1 / 65 Combinational Circuits  Output is function of input only i.e. no feedback When input changes, output may change (after a delay) n inputsm outputs Combinational Circuits 

3 2 / 65 Combinational Circuits  Analysis ●Given a circuit, find out its function ●Function may be expressed as: ♦ Boolean function ♦ Truth table  Design ●Given a desired function, determine its circuit ●Function may be expressed as: ♦ Boolean function ♦ Truth table ? ? ?

4 3 / 65 Analysis Procedure  Boolean Expression Approach ABC A+B+C AB+AC+BC (A’+B’)(A’+C’)(B’+C’) AB'C'+A'BC'+A'B'C F 1 =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC

5 4 / 65 Analysis Procedure  Truth Table Approach A B C F1F1 F2F =

6 5 / 65 Analysis Procedure  Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = A B C F1F1 F2F

7 6 / 65 Analysis Procedure  Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 = A B C F1F1 F2F

8 7 / 65 Analysis Procedure  Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = A B C F1F1 F2F

9 8 / 65 Analysis Procedure  Truth Table Approach = 1 = 0 = 1 = 0 = 1 = 0 = 1 = A B C F1F1 F2F

10 9 / 65 Analysis Procedure  Truth Table Approach = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 = A B C F1F1 F2F

11 10 / 65 Analysis Procedure  Truth Table Approach = 1 = 0 = 1 = 0 = 1 = 0 = 1 = A B C F1F1 F2F

12 11 / 65 Analysis Procedure  Truth Table Approach = A B C F1F1 F2F B 0101 A1010 C B 0010 A0111 C F 1 =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC

13 12 / 65 Design Procedure  Given a problem statement: ●Determine the number of inputs and outputs ●Derive the truth table ●Simplify the Boolean expression for each output ●Produce the required circuit Example: Design a circuit to convert a “BCD” code to “Excess 3” code  4-bits  0-9 values  4-bits  Value+3 ?

14 13 / 65 Design Procedure  BCD-to-Excess 3 Converter A B C D w x y z x x x x x x x x x x 1 1 x x C 111 B A xxxx 11 xx D C B A xxxx 1 xx D C B A xxxx 1 xx D C B A xxxx 1 xx D w = A+BC+BDx = B’C+B’D+BC’D’ y = C’D’+CDz = D’

15 14 / 65 Design Procedure  BCD-to-Excess 3 Converter A B C D w x y z x x x x x x x x x x 1 1 x x w = A + B(C+D) x = B’(C+D) + B(C+D)’ y = (C+D)’ + CD z = D’

16 15 / 65 Seven-Segment Decoder a b c g e d f ? wxyzwxyz abcdefgabcdefg w x y za b c d e f g x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 1 x x x x x x x y x w xxxx 11 xx z BCD code a = w + y + xz + x’z’b =... c =... d =...

17 16 / 65 Binary Adder  Half Adder ●Adds 1-bit plus 1-bit ●Produces Sum and Carry HA xyxy SCSC x y C S x + y ─── C S xyxy SCSC

18 17 / 65 Binary Adder  Full Adder ●Adds 1-bit plus 1-bit plus 1-bit ●Produces Sum and Carry x y z C S x + y + z ─── C S FA xyzxyz SCSC y 0101 x1010 z y 0010 x0111 z S = xy'z'+x'yz'+x'y'z+xyz = x  y  z C = xy + xz + yz

19 18 / 65 Binary Adder  Full Adder xyzxyz SCSC xyzxyz SCSC S = xy'z'+x'yz'+x'y'z+xyz = x  y  z C = xy + xz + yz

20 19 / 65 Binary Adder  Full Adder xyzxyz SCSC HA xyzxyz SCSC

21 20 / 65 Binary Adder c 3 c 2 c 1. + x 3 x 2 x 1 x 0 + y 3 y 2 y 1 y 0 ──────── Cy S 3 S 2 S 1 S 0 FA x 3 x 2 x 1 x 0 FA y 3 y 2 y 1 y 0 S 3 S 2 S 1 S 0 C 4 C 3 C 2 C 1 0 Binary Adder x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 S3S2S1S0S3S2S1S0 C0C0 CyCy Carry Propagate Addition

22 21 / 65 Binary Adder  Carry Propagate Adder CPA A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0 C0C0 CyCy CPA A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0 C0C0 CyCy x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 x 7 x 6 x 5 x 4 y 7 y 6 y 5 y 4 S 3 S 2 S 1 S 0 S 7 S 6 S 5 S 4 0

23 22 / 65 BCD Adder  4-bits plus 4-bits  Operands and Result: 0 to 9 + x 3 x 2 x 1 x 0 + y 3 y 2 y 1 y 0 ──────── Cy S 3 S 2 S 1 S 0 X +Y x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 SumCyS 3 S 2 S 1 S = = = = = = = = A = = Invalid Code Wrong BCD Value

24 23 / 65 BCD Adder X +Yx 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 SumCyS 3 S 2 S 1 S 0 Required BCD OutputValue = = = = = = = = = = = = = = = = = = = = 

25 24 / 65 BCD Adder  Correct Binary Adder’s Output (+6) ●If the result is between ‘A’ and ‘F’ ●If Cy = 1 S 3 S 2 S 1 S 0 Err S1S1 S2S2 S3S S0S0 Err = S 3 S 2 + S 3 S 1

26 25 / 65 BCD Adder Err

27 26 / 65 Binary Subtractor  Use 2’s complement with binary adder ●x – y = x + (-y) = x + y’ + 1

28 27 / 65 Binary Adder/Subtractor  M: Control Signal (Mode) ●M=0  F = x + y ●M=1  F = x – y

29 28 / 65 Overflow  Unsigned Binary Numbers  2’s Complement Numbers FA x 3 x 2 x 1 x 0 FA y 3 y 2 y 1 y 0 S 3 S 2 S 1 S 0 C 4 C 3 C 2 C 1 0 Carry FA x 3 x 2 x 1 x 0 FA y 3 y 2 y 1 y 0 S 3 S 2 S 1 S 0 C 4 C 3 C 2 C 1 0 Overflow

30 29 / 65 Magnitude Comparator  Compare 4-bit number to 4-bit number ●3 Outputs: ●Expandable to more number of bits Magnitude Comparator A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 A B

31 30 / 65 Magnitude Comparator

32 31 / 65 Magnitude Comparator A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 A B I (A>B) I (A=B) I (AB) I (A=B) I (A

33 32 / 65 Decoders  Extract “Information” from the code  Binary Decoder ●Example: 2-bit Binary Number Binary Decoder x1x0 x1x0 Only one lamp will turn on

34 33 / 65 Decoders  2-to-4 Line Decoder I 1 I 0 Y 3 Y 2 Y 1 Y Binary Decoder I1I0 I1I0 y3y2 y1y0 y3y2 y1y0

35 34 / 65 Decoders  3-to-8 Line Decoder Binary Decoder I2I1I0 I2I1I0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0

36 35 / 65 Decoders  “Enable” Control Binary Decoder I1I0E I1I0E Y3Y2 Y1Y0 Y3Y2 Y1Y0 EI 1 I 0 Y 3 Y 2 Y 1 Y 0 0x

37 36 / 65 Decoders  Expansion I 2 I 1 I 0 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y I 2 I 1 I 0 Binary Decoder I0I1E I0I1E Y3Y2 Y1Y0 Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 I0I1E I0I1E Y3Y2 Y1Y0 Y3Y2 Y1Y0

38 37 / 65 Decoders  Active-High / Active-Low I 1 I 0 Y 3 Y 2 Y 1 Y I 1 I 0 Y 3 Y 2 Y 1 Y Binary Decoder I1I0 I1I0 Y3Y2 Y1Y0 Y3Y2 Y1Y0 I1I0 I1I0 Y3Y2 Y1Y0 Y3Y2 Y1Y0

39 38 / 65 Implementation Using Decoders  Each output is a minterm  All minterms are produced  Sum the required minterms Example: Full Adder S(x, y, z) = ∑(1, 2, 4, 7) C(x, y, z) = ∑(3, 5, 6, 7) I2I1I0 I2I1I0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Binary Decoder xyz xyz S C

40 39 / 65 Implementation Using Decoders I2I1I0 I2I1I0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Binary Decoder xyz xyz S C I2I1I0 I2I1I0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Binary Decoder xyz xyz S C

41 40 / 65 Encoders  Put “Information” into code  Binary Encoder ●Example: 4-to-2 Binary Encoder x 3 x 2 x 1 y 1 y Binary Encoder y1y0 y1y0 x1x2x3 x1x2x3 Only one switch should be activated at a time

42 41 / 65 Encoders  Octal-to-Binary Encoder (8-to-3) I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 Y 2 Y 1 Y Binary Encoder Y2Y1Y0Y2Y1Y0 I7I6 I5I4I3I2 I1I0 I7I6 I5I4I3I2 I1I0

43 42 / 65 Priority Encoders  4-Input Priority Encoder I 3 I 2 I 1 I 0 Y 1 Y 0 V x x x x x x1 1 Priority Encoder VY1Y0VY1Y0 I3I2 I1I0I3I2 I1I0 Y1Y1 I1I I2I2 I3I I0I0

44 43 / 65 Encoder / Decoder Pairs Y2Y1Y0Y2Y1Y0 I7I6 I5I4I3I2 I1I0 I7I6 I5I4I3I2 I1I0 I2I1I0 I2I1I0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Binary Encoder Binary Decoder

45 44 / 65 Multiplexers MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 Y 0 I0I0 0 1I1I1 1 0I2I2 1 I3I3

46 45 / 65 Multiplexers  2-to-1 MUX  4-to-1 MUX MUX Y I0I1I0I1 S Y I0I1 I2I3I0I1 I2I3 S 1 S 0

47 46 / 65 Multiplexers  Quad 2-to-1 MUX MUX Y I0I1I0I1 S Y I0I1I0I1 S Y I0I1I0I1 S Y I0I1I0I1 S x3x2x1x0 x3x2x1x0 y3y2y1y0 y3y2y1y0 S A3A2 A1A0A3A2 A1A0 S E Y3Y2 Y1Y0Y3Y2 Y1Y0 B3B2 B1B0B3B2 B1B0

48 47 / 65 Multiplexers  Quad 2-to-1 MUX MUX A3A2 A1A0A3A2 A1A0 S E Y3Y2 Y1Y0Y3Y2 Y1Y0 B3B2 B1B0B3B2 B1B0 Extra Buffers

49 48 / 65 Implementation Using Multiplexers MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 x yF  Example F(x, y) = ∑(0, 1, 3) x y F

50 49 / 65 Implementation Using Multiplexers x y zF  Example F(x, y, z) = ∑(1, 2, 6, 7) MUX Y I0I1 I2I3I4I5 I6I7I0I1 I2I3I4I5 I6I7 S 2 S 1 S 0 x y z F

51 50 / 65 Implementation Using Multiplexers MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 x y zF  Example F(x, y, z) = ∑(1, 2, 6, 7) x y F F = z z z F = 0 0 F = 1 1

52 51 / 65 MUX Y I0I1 I2I3I4I5 I6I7I0I1 I2I3I4I5 I6I7 S 2 S 1 S 0 Implementation Using Multiplexers A B C DF  Example F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15) A B C F F = D D D D F = 0 0 F = D F = 1 0 D 1 1

53 52 / 65 Y I0I1 I2I3I4I5 I6I7I0I1 I2I3I4I5 I6I7 S 2 S 1 S 0 Multiplexer Expansion  8-to-1 MUX using Dual 4-to-1 MUX MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 MUX Y I0I1I0I1 S 0 1

54 53 / 65 DeMultiplexers DeMUX I Y3Y2Y1Y0Y3Y2Y1Y0 S 1 S 0 Y 3 Y2Y2 Y1Y1 Y0Y I 0 100I0 1 00I00 1 I000

55 54 / 65 Multiplexer / DeMultiplexer Pairs Y I7I6 I5I4I3I2 I1I0 I7I6 I5I4I3I2 I1I0 I Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 MUXDeMUX S 2 S 1 S 0 x 2 x 1 x 0 y 2 y 1 y 0 Synchronize

56 55 / 65 DeMultiplexers / Decoders Binary Decoder I1I0E I1I0E Y3Y2 Y1Y0 Y3Y2 Y1Y0 EI 1 I 0 Y 3 Y 2 Y 1 Y 0 0x DeMUX I Y3Y2Y1Y0Y3Y2Y1Y0 S 1 S 0 Y 3 Y2Y2 Y1Y1 Y0Y I 0 100I0 1 00I00 1 I000

57 56 / 65 Three-State Gates  Tri-State Buffer  Tri-State Inverter AY C C AY 0 xHi-Z AY C

58 57 / 65 Three-State Gates A Y C B D C DY 0 Hi-Z 0 1B 1 0A 1 ? Not Allowed Y=Y= A C B A if C = 1 B if C = 0

59 58 / 65 Three-State Gates I0I0 Y E S1S1 I1I1 I2I2 I3I3 Binary Decoder I1I0E I1I0E Y3Y2 Y1Y0 Y3Y2 Y1Y0 S0S0

60 59 / 65 Homework  Mano ●Chapter 4 ♦ 4-2 ♦ 4-3 ♦ 4-5 ♦ 4-11 ♦ 4-13 ♦ 4-27 ♦ 4-28 ♦ 4-31 ♦ 4-32 ♦ 4-33 ♦ 4-35

61 60 / 65 Homework  Mano 4-2Obtain the simplified Boolean expressions for output F and G in terms of the input variables in the circuit:

62 61 / 65 Homework 4-3For the circuit shown in the “Quad 2-to-1 MUX”: (a) Write the Boolean functions for the four outputs in terms of the input variables (b) If the circuit is listed in a truth table, how many rows and columns would there be in the truth table? 4-5Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less than the input.

63 62 / 65 Homework 4-11Design a 4-bit combinational circuit incrementer. (A circuit that adds one to a 4-bit binary number.) The circuit can be designed using four half-adders. 4-13The adder-subtractor circuit has the following values for mode input M and data inputs A and B. In each case, determine the values of the four SUM outputs and the carry C. M A B (a) (b) (c) (d) (e)

64 63 / 65 Homework 4-27A combinational circuit is specified by the following three Boolean functions: F 1 (A, B, C) = ∑(2, 4, 7) F 2 (A, B, C) = ∑(0, 3) F 3 (A, B, C) = ∑(0, 2, 3, 4, 7) Implement the circuit with a decoder constructed with NAND gates and NAND or AND gates connected to the decoder outputs. Use a block diagram for the decoder. Minimize the number of inputs in the external gates.

65 64 / 65 Homework 4-28A combinational circuit is defined by the following three Boolean functions: F 1 = x’ y’ z’ + x z F 2 = x y’ z’ + x’ y F 3 = x’ y’ z + x y Design the circuit with a decoder and external gates Construct a 16  1 multiplexer with two 8  1 and one 2  1 multiplexers. Use block diagrams. 4-32Implement the following Boolean function with a multiplexer: F(A, B, C, D) = ∑(0, 1, 3, 4, 8, 9, 15)

66 65 / 65 Homework 4-33 Implement a full adder with two 4  1 multiplexers: 4-35 Implement the following Boolean function with a 4  1 multiplexer and external gates. Connect inputs A and B to the selection lines. The input requirements for the four data lines will be a function of variables C and D. These values are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01, 10, and 11. These functions may have to be implemented with external gates. F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)


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