Presentation on theme: "EE2301: Basic Electronic Circuit Recap in last lecture EE2301: Block B Unit 21."— Presentation transcript:
EE2301: Basic Electronic Circuit Recap in last lecture EE2301: Block B Unit 21
EE2301: Block C Unit 12 p-n Junction The pn junction forms the basis of the semiconductor diode Within the depletion region, no free carriers exist since the holes and electrons at the interface between the p-type and n-type recombine.
EE2301: Block C Unit 13 Diode Symbol and Operation Forward-biased Current (Large) Reverse-biased Current (~Zero) + - Forward Biased: Diode conducts - + Reverse Biased: Little or no current iDiD
EE2301: Block C Unit 14 Ideal diode model Circuit containing ideal diode Circuit assuming that the ideal diode conducts Circuit assuming that the ideal diode does not conduct
EE2301: Block C Unit 15 Rectification: from AC to DC Supply is ACDC required One common application of diodes is rectification. In rectification, an AC sinusoidal source is converted to a unidirectional output which is further filtered and regulated to give a steady DC output.
EE2301: Block C Unit 16 Rectifier with regulator diagram Rectifier Bi-directional input Steady DC output Filter Regulator Unidirectional output We will look at two types of rectifiers and apply the large signal models in our analysis: 1) Half wave rectifier 2) Full wave rectifier
EE2301: Basic Electronic Circuit Starting from this lecture EE2301: Block B Unit 27
Unit 88 The Transistor A transistor is a 3-terminal semiconductor device (cf Diode is a 2-terminal device) Performs 2 main functions fundamental to electronic circuits: 1)Amplification – magnifying a signal 2)Switching – controlling a large current or voltage across 2 terminals (on/off) 2 major families of transistors: 1)Field Effect Transistors (FETs) – Unit 2 2)Bipolar Junction Transistors (BJTs) – Unit 3
Unit 89 Transistors as Switches (1) Controlling I or V I or V applied at 3 rd terminal switches the device on/off Controlling I or V
Unit 810 Transistors as Amplifiers (1) Gain is determined by I or V applied at 3 rd terminal v in v out Controlling I or V
EE2301: Block C Unit 212 Block C - Unit 2 Outline MOSFET operation > Construction of the MOSFET > Basic working principle of the MOSFET > Operating modes of the MOSFET MOSFET amplifiers (In this course, the focus will be on their use in amplifier circuits) > Biasing the MOSFET > Small signal equivalent circuit
EE2301: Block C Unit 213 Transistors as Amplifiers Whereas a diode is a 2 terminal device, transistors in contrast have 3 terminals. In a diode, the current is controlled by the voltage across the diode. For transistors, the current through the device is controlled by the voltage across the device as well as the voltage or current applied to a 3 rd port. BJT FET Unit 3 Unit 2
EE2301: Block C Unit 214 Classification of FETs FET: Field Effect Transistor JFET: Junction FET MOSFET: Metal Oxide Semiconductor FET
EE2301: Block C Unit 215 Enhancement mode MOS Bulk (substrate) Gate SourceDrain Metal Oxide Semiconductor p G D S n+n+ n+n+ The above figure shows an n-channel enhancement mode MOS (also known as NMOS) with its respective symbol. It contains three terminals: Source (S), Gate (G) and Drain (D). When in operation, the current flows between the source and drain. The carriers move in the direction from the source to the drain. This current is controlled by the voltage applied to the gate. In the symbol, the arrow points towards the gate for n-channel MOS. For NMOS, the source and drain are n-type, while the bulk substrate is p-type.
EE2301: Block C Unit 216 Enhancement NMOS Operation Bulk (substrate) G SD p G D S n+n+ n+n+ I D : Channel current - V GD + +V GS - Amount of current in the channel is controlled by the voltage applied at the terminals (V GS and V GD ) Device is “switched on” (formation of a conducting channel) by the voltage on the Gate IDID
EE2301: Block C Unit 217 Gate Current Bulk (substrate) G SD p n+n+ n+n+ G D S Gate current sees a capacitor formed by the gate, oxide (which is insulating), and substrate (conducting) I G =0 Gate Oxide Substrate I G =0
EE2301: Block C Unit 218 NMOS is normally off Bulk (substrate) G SD p n+n+ n+n+ +_+_ V DD When no voltage is applied to the gate, the enhancement mode NMOS will not conduct between S and D (even for a voltage applied across S and D). This is because, as we can see from the figure on the right: Drain-Bulk n + p junction is strongly reverse-biased Source-Bulk n + p junction is also reverse-biased No undisrupted conductive path between source and drain: no current V DD When V GS = 0V, I D = 0A Reverse-biased S D
EE2301: Block C Unit 219 Conducting channel in NMOS G D S +_+_ iDiD V DD A key point on MOS devices is that for the device to conduct (or turn on), there must be a conducting channel between the source and drain. For NMOS, this channel must be n-type. For this n-channel to form, V GS must be larger than V T, which is known as the threshold voltage. The value of VT depends on the design and properties of the device. +_+_ V GG Bulk (substrate) G SD p n+n+ n+n+ +-+- V DD +-+- V GG For conduction to occur, V GS > V T
EE2301: Block C Unit 220 Formation of channel in NMOS V GG (+ve) + + + + + + _ _ _ _ _ _ _ When V GS > V T : The minority carriers in p-type silicon are electrons (negatively charged) Electrons are attracted towards the surface at the silicon-oxide interface A narrow conducting n-type channel near this surface forms Electrons from the source can now flow towards the drain resulting in a a drain current I D Increasing V GS (while keeping V DS fixed) increases the concentration of carriers, thereby increasing conduction p-type substrate Initially when V GS < V T : The majority carriers in p-type silicon are holes (positively charged) Holes are repelled away from the surface at the silicon-oxide interface The interface becomes depleted of majority carriers No conduction occurs between S and D
EE2301: Block C Unit 221 p-Channel MOS (PMOS) The PMOS operates on the same principle as the NMOS only that the charge carrier types are reversed. As a consequence of this swap: (1)It is p-type conducting channel that is formed in an n-type bulk (2)It requires a negative threshold voltage in order to form the channel p
EE2301: Block C Unit 222 Enhancement vs Depletion mode Enhancement mode Only when V GS is greater than V T will a conducting channel form at the surface of the bulk as free charge carriers are created, otherwise device remains off. As such, we say the device is normally off. Depletion mode In contrast, depletion mode MOS devices are designed with a built-in conducting channel. Hence even with no gate voltage, the MOS will still conduct between source and drain. The device is turned off by applying a gate voltage so as to deplete this channel. In this course we will focus on the enhancement mode MOS, which we shall see has three regions of operation unlike the diode which has only 2 (either on or off).
EE2301: Basic Electronic Circuit Different Operation Regions of a MOSFET Device Con’t in next lecture EE2301: Block B Unit 223
EE2301: Block C Unit 224 Cutoff mode Cutoff Region V GS and V GD both less than V T Channel is off at both source and drain No conduction and no current flow between S & D D S G Cutoff Region V GS < V T, V GD < V T As a result of this, I D = 0A IDID The first mode we shall consider is when the device is off. This is known as Cutoff. As previously pointed out, this occurs when the threshold voltage has not been reached.
EE2301: Block C Unit 225 Triode mode Triode/Ohmic Region Both V GS and V GD are greater than V T Channel is on at source and also on at drain Current is dependent of both V DS and V GS Triode/Ohmic Region V GS > V T, V GD > V T The drain current is given by: I D = K [2(V GS – V T )V DS – V DS 2 ] D S G IDID As mentioned previously, when the gate voltage exceeds the threshold the MOS can conduct and therefore turns on. When it turns on, it can operate in one of two possible regions. One of these 2 modes is known as the triode or ohmic region. K is known as the conductance parameter, and is defined as: W: channel width L: channel length µ: mobility of carriers C ox : Oxide capacitance
EE2301: Block C Unit 226 MOS in Triode mode Bulk (substrate) G SD p n+n+ n+n+ +_+_ V DD V GS > V T V GD > V T Near both the drain and source: Voltage difference > V T Conducting channel is formed on both sides In fact everywhere under the gate oxide is larger than V T so there is a continuous channel between the drain and source. Increasing V GS thus increases the number of carriers, resulting in a larger drain current Increase V DS increases the voltage drop across the channel, resulting in a larger drain current I D is dependent therefore on both V DS and V GS (Refer to equation on previous slide)
EE2301: Block C Unit 227 Saturation mode Saturation Region V GS > V T and V GD < V T Channel is on at source but off at drain Current is nearly independent of V DS, depending only on V GS One might expect the MOS to operate like in cutoff under these bias conditions but it does not. Saturation Region V GS > V T, V GD < V T The drain current is given by: i D = K (V GS – V T ) 2 D S G - V GD + +V GS - IDID While the MOS is still on, if we continue to increase V DS without increasing V GS, there will come a point when the voltage near the drain becomes less than the threshold (V GD < V T ). This is known as the saturation region.
EE2301: Block C Unit 228 NMOS in Saturation Bulk (substrate) G SD p n+n+ n+n+ +-+- V DD +-+- V GG Pinch-off (going from triode to saturation) The channel near the drain begins for fall below the threshold condition when V GD = V T In terms of the drain-source voltage, this corresponds to: V DS (pinch-off) = V GS - V T The channel in saturation mode is typically represented as tapered or wedged (as shown in the figure). Large currents still conduct via the channel due to the large voltage drop across drain and source, but changes little with increasing V DS.
EE2301: Block C Unit 229 Summary of operating modes For n-channel enhancement MOS Cut-Off: V GS < V T, V GD V T, V GD > V T Saturation: V GS > V T, V GD < V T
EE2301: Block C Unit 230 Operating Regions CUTOFF I D = K V DS 2 TRIODE/OHMIC SATURATION BREAKDOWN When V GS - V T = V DS
Operating state example EE2301: Block C Unit 231 Determine the operating state of the MOSFET shown in the circuit for the given values of V DD and V GG if the ammeter and voltmeter shown read the following values: a.V GG = 1V; V DD = 10V; I D = 0mA; R D = 100Ω b.V GG = 4V; V DD = 10V; I D = 72mA; R D = 100Ω c.V GG = 6V; V DD = 10V; I D = 270mA; R D = 26Ω For the MOSFET in the circuit, V T = 2V; K = 18mA/V 2 a. Drain current is zero, which implies that the MOS is in the cutoff state. We should also check that V GS and V GD are both less than V T. V GS = 1V V GD = - 9V
Operating state example EE2301: Block C Unit 232 b. V GS = 4V (hence larger than V T ); we now still need to find V GD to decide whether the MOS is in the triode or saturation region. V DS = V DD – I D R D = 2.8V V GD = V GS – V DS = 1.2V (less than V T ) MOS is in saturation c. V GS = 6V (hence larger than V T ); we now still need to find V GD to decide whether the MOS is in the triode or saturation region. V DS = V DD – I D R D = 3V V GD = V GS – V DS = 3V (larger than V T ) MOS is in the ohmic region
MOSFET Q-point EE2301: Block C Unit 233 As mentioned at the start, in this course our focus is on the use of transistors for amplifiers. A key takeaway to remember is that when building an amplifier, we use the saturation region. Why this is so will become clear in the next few slides. For this to be realized, the MOS amplifier circuit has to be designed to ensure the MOS is working at the operating point (which corresponds to a fixed value of I D, V GS and V DS ). This is called the Q-point. We say that the circuit needs to be properly biased to give us the desired Q-point.
Determining Q-point (Graphical) EE2301: Block C Unit 234 The I-V characteristic of the MOS describes the full range of values that the MOS can take. However, the MOS works only at one value of I D, V DS and V GS when put in a circuit. It is the circuit that imposes this constraint on the MOS. Hence to find the Q-point we also need to consider the characteristics of the circuit as well: this is defined by the load line. The Q-point is found at the intersection of the load line and the I-V curve. Load line: Apply KVL around the right side mesh, V DD = V DS + I D R D Since we want to draw this on the I-V curve, we should express this as I D against V DS : I D = V DD /R D – V DS /R D Given: V GG = 2.4V; V DD = 10V; R D = 100Ω
MOSFET amplifiers EE2301: Block C Unit 235 But how do we achieve the function of an amplifier from the concept of the Q-point? We can see this graphically. Initially, V GS = 2.4V, while I D = 52mA and V DS = 4.75V Now if V GS was dropped slightly by 0.2V, then V DS ≈ 6.4V (+1.65V) Now if V GS was instead increased from 2.4V by 0.2V, V DS 2.8V (-1.95V) V GG forms the input and V D is the output We see that for a peak to peak change in the input by 0.4V, we see a peak to peak change in the output by 3.6V Output is amplified!
Find Q-point by calculation EE2301: Block C Unit 236 We have seen how to determine the Q-point of the MOS graphically. This example shows how we can do the same but now using calculation. Given: V GG = 2.4V; V DD = 10V; R D = 100Ω; V T = 1.4V; K = 52mA/V 2 Since the source is connected to ground, it becomes obvious that V GS = 2.4V Now we still need to find V DS and I D (2 equations). To do so we can apply KVL around the right-hand mesh. To get another equation, we use the formula to find I D when MOS is in saturation (this is a lot simpler than that for triode state). Applying KVL to right-hand mesh: V DD = V DS + I D R D 10 = V DS + 0.1*I D Next, we use the drain current formula for saturation mode: I D = K(V GS – V T )2 I D = 52*(2.4 – 1.4) 2 = 52mA From this, we can then find V DS V DS = 4.8V Is it saturation? Check: V GD = -2.4V (less than V T ) YES!!
EE2301: Basic Electronic Circuit Recap in last lecture EE2301: Block B Unit 237
EE2301: Block C Unit 238 Summary of operating modes For n-channel enhancement MOS Cut-Off: V GS < V T, V GD V T, V GD > V T Saturation: V GS > V T, V GD < V T
EE2301: Block C Unit 239 Operating Regions TRIODE/OHMIC SATURATION BREAKDOWN CUTOFF
Biasing aMOSFET (Q-point) EE2301: Block C Unit 240 V GS =2.4V, V DS =4.75V V GS =2.2V, V DS =2.8V V GS =2.6V, V DS =6.4V Vpp = 3.6V Vpp =0.4V A change in V GS is AMPLIFIED by 9 times in V DS !!
EE2301: Basic Electronic Circuit Let’s con’t EE2301: Block B Unit 241
Self-biasing MOS amplifier EE2301: Block C Unit 242 Determine V GS, V DS, and I D for the following MOS amplifier, given that: R 1 = R 2 = 1MΩ; R D = 6kΩ; R S = 6kΩ; V DD = 10V; V T = 1V; K = 0.5mA/V 2 Begin by first finding the gate voltage: Next we assume the MOS is in saturation and then check to see if this assumption (V GS >V T and V GD
"name": "Self-biasing MOS amplifier EE2301: Block C Unit 242 Determine V GS, V DS, and I D for the following MOS amplifier, given that: R 1 = R 2 = 1MΩ; R D = 6kΩ; R S = 6kΩ; V DD = 10V; V T = 1V; K = 0.5mA/V 2 Begin by first finding the gate voltage: Next we assume the MOS is in saturation and then check to see if this assumption (V GS >V T and V GD
Self-biasing MOS amplifier EE2301: Block C Unit 243 Only one of these solutions is valid for our case: thus we need to check each one in turn to see which of these makes physical sense. But what do we use I D to check for? A hint is that we still have not found the value of V DS up till this point. We have assumed that it is a value that corresponds to the saturation mode. We can substitute I D into the right-hand mesh to find V DS since we can see that: V DD = V DS + I D (R D + R S ) First we try I D = 0.89mA: V DS = 10 – 0.89*12 = -0.68V (REJECTED: V DS should be positive) Now we try I D = 0.5mA: V DS = 10 – 0.5*12 = 4V (ACCEPTED: this makes sense) Finally, now that we know V DS, we can then use this information to verify if our starting assumption (that the MOS is in saturation) was true. To do this, we find V GD : V GD = V G – (V DS + I D R S ) = 5 – (4 + 0.5*6) = -2V V T This indicates the MOS is in saturation, thereby confirming our starting assumption.
Example (Prob 11.9) The NMOS transistor shown in figure has V T =1.5V and K=0.4mA/V 2. If V G is a pulse with 0 to 5V, find the voltage levels of the pulse signal at the drain output. Assume the NMOS is in saturation region when V G =5V EE2301: Block C Unit 244 Since V T = 1.5 V, with v G = 0 V, v GS < V T, the transistor is cut off. Therefore, v D = 5 V. When v G = 5 V, and assuming that the transistor is in the saturation region: i D = k (v GS - V T )2 = 0.4 (5 - 1.5)2 = 4.9 mA. Therefore, v D = 5 - 4.9´1 = 0.1 V.
Small signal equivalent circuit The MOS is inherently a non-linear device (basic circuit theory is based on linear problems) Within a small range, we see from the I-V characteristic that we can approximate its behavior as linear This allows us to analyze a MOS amplifier using the I-V graph We can instead define the linear characteristics of the MOS for a given Q-point We can do so using a small signal equivalent circuit Now we can analyze the MOS using the linear circuit theory we have learnt so far EE2301: Block C Unit 245
Small signal equivalent circuit Linearizes the characteristics of a MOSFET (which is otherwise nonlinear) for a given operating point Only valid for a particular operating point Only valid for small varying signals EE2301: Block C Unit 246 i d = g m v gs + v ds /r o rdrd Mathematics will not covered in this course
EE2301: Basic Electronic Circuit End of Block C Unit 2 EE2301: Block B Unit 247