Download presentation
Presentation is loading. Please wait.
1
ECA1212 Introduction to Electrical & Electronics Engineering Chapter 6: Field Effect Transistor by Muhazam Mustapha, October 2011
2
Learning Outcome By the end of this chapter students are expected to:
Be able to explain some basic physical theory and operation of FET Be able to do calculation on DC and AC analysis on FET circuit
3
Chapter Content Theory of FET FET Operation FET in Digital Circuit
4
Field Effect Transistor
CO1
5
Field Effect Transistor
FET is a piece of electronic device that conducts electricity by the control of a gate It can be considered as a voltage controlled resistor or voltage controlled current source Current flows through the center body of channel from terminals called drain to source Gate is a plate not touching the substrate Drain Gate Channel Source CO1
6
FET Types There are many types of FET We will cover mostly NMOS
MOSFET – Metal Oxide Semiconductor FET JFET – Junction FET NMOS – n-channel MOSFET PMOS – p-channel MOSFET We will cover mostly NMOS CO1
7
Channel Types FET is also characterized by its channel n-channel
The majority carrier in the channel is electron p-channel The majority carrier in the channel is hole CO1
8
Modes Enhancement mode Depletion mode
FET is normally NOT conducting current even when given voltage at drain and source Gate is to increase the current Depletion mode FET is normally conducting current when given voltage at drain and source Gate is to decrease the current CO1
9
Depletion Mode p-channel
Current flow is reduced by putting a positive voltage at gate to repel holes flow and finally block the current The more positive the gate, the less current flow Drain +ve Gate Hole Flow +ve p-channel Gate’s electric field repelling holes −ve Source CO1
10
Depletion Mode n-channel
Current flow is reduced by putting a negative voltage at gate to repel electrons flow and finally block the current The more negative the gate, the less current flow Drain +ve Gate Electron Flow −ve n-channel Gate’s electric field repelling electrons −ve Source CO1
11
Enhancement Mode (PMOS)
n-substrate p-channel When negative voltage is put to drain that is made of highly p dopant (p+), reverse bias junction is formed at drain – hence no current flows Negative voltage is put to gate to attract holes and effectively compensate the reverse biases – until current can flow Drain p-channel formation −ve p+ Gate Hole Flow −ve p+ Gate’s electric field attracting holes +ve Source CO1
12
Enhancement Mode (NMOS)
p-substrate n-channel When positive voltage is put to drain that is made of highly n dopant (n+), reverse bias junction is formed at drain – hence no current flows Positive voltage is put to gate to attract electrons and effectively compensate the reverse biases – until current can flow Drain n-channel formation +ve n+ Gate Electron Flow +ve n+ Gate’s electric field attracting electrons −ve Source CO1
13
Circuit Symbol and Notations
Depletion Enhancement JFET p-channel n-channel CO1
14
Operation Region CO1
15
I-V Characteristic CO1 ID, mA VGS = 5.0V Ohmic Region 15 10 5 0
VGS = 4.5V Saturation Region VGS = 4.0V VGS = 3.5V VGS = 3.0V VGS = 2.5V VDS, V Cutoff Region CO1
16
Operation Region Cutoff Ohmic / Triode VGS < VT and VGD < VT
No current flow Ohmic / Triode VGS > VT and VGD > VT Linear I-V characteristic CO1
17
Operation Region Saturation VGS > VT and VGD < VT
ID is controlled by VGS (Saturation Region Formula): Conductance parameter Threshold voltage – minimum voltage to form a conducting channel CO1
18
FET In Digital Circuit CO1
19
NAND, NOR and NOT Gates CO1
Similar presentations
![EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]](/16/5062541/big_thumb.jpg "EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]>")
