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ENGR-43_Lec-12a_FETs-1.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical.

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Presentation on theme: "ENGR-43_Lec-12a_FETs-1.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical."— Presentation transcript:

1 ENGR-43_Lec-12a_FETs-1.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical & Mechanical Engineer Engineering 43 FETs-1 (Field Effect Transistors)

2 ENGR-43_Lec-12a_FETs-1.pptx 2 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Learning Goals Understand the Basic Physics of MOSFET Operation Describe the Regions of Operation for a MOSFET Device Use the Graphical LOAD-LINE method to analyze the operation of basic MOSFET Amplifiers Determine the LARGE-SIGNAL Bias- Point (Q-Point) for MOSFET circuits

3 ENGR-43_Lec-12a_FETs-1.pptx 3 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Learning Goals Use SMALL-SIGNAL models to analyze various FET Amplifiers Calculate Performance Metrics for various FET Amplifiers Apply FETs to the Design and Construction of CMOS Logic Gates

4 ENGR-43_Lec-12a_FETs-1.pptx 4 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Transistor What is it? Transistor is a contraction for Transfer Resistor These devices have THREE connections: Input Output Control The transistors Fluidic-Analog is a Metering (Needle) Valve (a Faucet)

5 ENGR-43_Lec-12a_FETs-1.pptx 5 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The concept of voltage-controlled resistance An independent Voltage Applied to the Control connection (the Gate) regulates the flow of Current Thru the device Gate Drain (or Source) Source (or Drain)

6 ENGR-43_Lec-12a_FETs-1.pptx 6 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Flavors of FETS Junction Field Effect Transistor JFET A Normally ON transistor Reverse Biasing two PN Junctions will Pinch Off a Conducting Channel

7 ENGR-43_Lec-12a_FETs-1.pptx 7 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Flavors of FETS Depletion Mode MOSFET Another Normally ON transistor Applying a Gate Voltage Drives Carriers OUT of the conducting Channel to turn off the transistor No direct GateChannel Connection –An Isulated Gate Field Effect Transistor (IGFET)

8 ENGR-43_Lec-12a_FETs-1.pptx 8 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Flavors of FETS Enhancement Mode MOSFET Normally OFF transistor Another IGFET Applying a Gate Voltage Attracts & Creates carriers to FORM a conducting Channel to turn ON the transistor These Make Great Switches

9 ENGR-43_Lec-12a_FETs-1.pptx 9 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MOSFET What does that mean? M Metal O Oxide S Silicon F Field E Effect T Transistor Short for Transfer Resistor

10 ENGR-43_Lec-12a_FETs-1.pptx 10 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Enhancement Mode - IGFET Insulated Gate Field Effect Transistors are Normally-Off devices Applying a Positive Voltage to the Gate will attract e to the Channel This will eventually invert a thin region below the gate to N-type, creating a conducting channel between S & D IGFETs are Great Switches Used in almost all digital ICs Back-to-Back PN Jcns Between source & drain

11 ENGR-43_Lec-12a_FETs-1.pptx 11 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MOSFET Nomenclature & Dims We will consider only Enhancement FETs n+ Heavily Doped n-Type An n-Channel (nFET) enhancement mode FET

12 ENGR-43_Lec-12a_FETs-1.pptx 12 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MOSFET: Current & Speed In General the performance of an Enhancement Mode MOSFET Current Carrying Capacity Increases with Increasing Width, W On/Off Switching Speed Increases with Decreasing Gate Length, L –As of 2011 the minimum (best) value for L was about 22 nm

13 ENGR-43_Lec-12a_FETs-1.pptx 13 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MOSFET On/Off Operation SourceDrain SiO 2 Insulator (Glass) Gate holes electrons 5 volts electrons to be transmitted Step 1: Apply Gate Voltage Step 2: Excess electrons surface in channel, holes are repelled. Step 3: Channel becomes saturated with electrons. Electrons in source are able to flow across channel to Drain. P NN

14 ENGR-43_Lec-12a_FETs-1.pptx 14 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis nMOSFET Circuit Symbol n-Channel MOSFET electrons move from SourceDrain to produce the Drain Current PN Junction forms between Substrate and Channel when FET is ON

15 ENGR-43_Lec-12a_FETs-1.pptx 15 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MOSFET Operation: CutOff As seen in previous diagrams, unpowered MOSFETS have two OPOSING PN junctions ChannelSource ChannelDrain With NO Potential applied to the gate No current can flow From the Previous slide the Minimum Gate Voltage required for current-flow is called the Threshold Voltage, V to or V th A MOSFET with V GS < V th is CutOff i.e.; The MOSFET is Off, and the Drain Current, i D = 0

16 ENGR-43_Lec-12a_FETs-1.pptx 16 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MOSFET Circuit in CutOff The Diagram at Right shows an nMOSFET in CutOff For v GS

17 ENGR-43_Lec-12a_FETs-1.pptx 17 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Power MOSFET Data Sheet

18 ENGR-43_Lec-12a_FETs-1.pptx 18 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis CutOff Summarized V GS < V to No Drain Current Flows

19 ENGR-43_Lec-12a_FETs-1.pptx 19 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MOSFET IN Triode (Ohmic) Region In this case the nMOSFET Voltage conditions: Electrons are ATTRACTED to the Positive-Gate and a thin Conducting Channel Forms In this Region the Drain Current depends on BOTH v DS and v GS Fluid Analogy needle valve

20 ENGR-43_Lec-12a_FETs-1.pptx 20 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis nMOSFET in Triode Operation When v GS > V to a conducting channel forms below the gate

21 ENGR-43_Lec-12a_FETs-1.pptx 21 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Triode Operation When v GS > V to a conducting channel forms below the gate. That is the type of the silicon is INVERTED from p-Type to n-Type –Thus this conducting Channel is often called an Inversion Layer The greater v GS The more the conducting the channel becomes The Channel resistance is a fcn of v GS

22 ENGR-43_Lec-12a_FETs-1.pptx 22 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Triode Operation In the Triode Region, i D increases for Increasing v GS Increasing v DS Thus current thru the device depends on the voltage at ALL three connections as long as v DS < (v GS V to ) The Three- Connection dependency is why this region is called TRIODE

23 ENGR-43_Lec-12a_FETs-1.pptx 23 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Triode Operation In Triode Operation, the i D curve is a concave-down Parabola given by Where The Device Transconductance Parameter, KP, Depends on the Construction of the FET KP for nFETs is typically µA/V 2

24 ENGR-43_Lec-12a_FETs-1.pptx 24 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis PinchOff In order to form a complete channel, every point, x, along the channel must have a voltage difference greater than V to That is, need The greater this qty, the thicker the conducting Layer Now as v DS is increased eventually at x = L where v chan = v DS The Channel Thickness goes to ZERO. This is called PINCH-OFF

25 ENGR-43_Lec-12a_FETs-1.pptx 25 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis PinchOff Illustrated The layer is THICKEST at the Source and ZERO at the Drain when Thus Have PinchOff when At this Point the channel is Very Thick at the Source- End, and Zero-Thick at the Drain End Pinched Off at Drain

26 ENGR-43_Lec-12a_FETs-1.pptx 26 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis TriOde Region Summarized v DS (v GS V to ) i D = f(v DS, V GS ) Start of TriOde Channel Formation Finish of TriOde Drain PinchOff

27 ENGR-43_Lec-12a_FETs-1.pptx 27 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis PinchOff i D Saturation As v DS increases the PinchOff Point, x pop, Moves BACKWARDS towards the Source Once the channel Pinches Off, the drain current, i D, NO Longer increases with increasing v DS In other words, for a given v GS, the Current Saturates (stays constant) After PinchOff as shown below

28 ENGR-43_Lec-12a_FETs-1.pptx 28 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis nMOSFET complete vi Curve

29 ENGR-43_Lec-12a_FETs-1.pptx 29 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MOSFET Operation Summary 1.Cut-Off Region – In this region the gate voltage is less than the Threshold voltage V to and therefore very little current flows. 2.Triode Region – In this mode the device is operating below pinch-off and is effectively a variable resistor. 3.Saturation Region – This is the main operating region for the device. The drain voltage has to be greater than the gate voltage minus the Threshold voltage.

30 ENGR-43_Lec-12a_FETs-1.pptx 30 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Operation in Saturation Notice that in SAT i D varies with v GS Note that v DS does NOT appear in this Equation v DS (on vi curve) does NOT affect i D after Channel-PinchOff In SAT a MOSFET is true 3-terminal device; current depends ONLY on the CONTROL Signal, v GS

31 ENGR-43_Lec-12a_FETs-1.pptx 31 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Saturation Summarized v DS (v GS V to ) i D f(v DS ) PinchOff Moved BACK from Drain

32 ENGR-43_Lec-12a_FETs-1.pptx 32 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis TriodeSaturation Boundary At the boundary Line the nMOSFET just Barely Pinches Off at the Drain end thus: By KVL Substituting Find Or at the Boundary Boundary Line Sub for v GS into i D,sat Eqn

33 ENGR-43_Lec-12a_FETs-1.pptx 33 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

34 ENGR-43_Lec-12a_FETs-1.pptx 34 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis TriodeSaturation Boundary Then then i D along the Boundary The Boundary is described by a Concave-UP Parabola that passes thru the origin Boundary Line

35 ENGR-43_Lec-12a_FETs-1.pptx 35 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example 12.1 make vi Plot Use Parameters from Example 12.1 to plot in MATLAB the vi Curve for an nMOSET The Parameters W = 160 µm L = 2 µm (pretty large) KP = 50 µA/V 2 V to = 2V Plot has multiple operating regions must concatenate

36 ENGR-43_Lec-12a_FETs-1.pptx 36 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The completed Plot

37 ENGR-43_Lec-12a_FETs-1.pptx 37 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MATLAB Code-1 % Bruce Mayer, PE % ENGR43 * 14Jan12 % file = nMOSFET_Plot_ex12_1_1201.m W = 160; % µm L = 2; % µm KP = 50; % µA/sq-V Vto = 2' % V % % calc Parameter K K = (W/L)*KP/2; % µA/sqV) % % set vGS values that exceed CutOff at 2V vGS = [3, 4, 5, 6]; % % calc boundary Triode/Sat boundary by finding iD at the START of sat % region iDsat_uA = K*(vGS-Vto).^2; % in µA iDsat_mA = iDsat_uA/1000 % % show cutoff line vDSco = linspace(0,10, 200); iDco = zeros(200); % DeBug Command => plot(vDSco, iDco, 'LineWidth', 3) % % Calc iD in Triode Region for vGS>Vto (Pinched off at Drain) %* use eqn (12.6) in text vDSsat = sqrt(iDsat_uA/K) % must take care with units % plot(vDSsat,iDsat_mA, '--*', 'LineWidth', 3), grid, xlabel('vDSsat'), ylabel('iDsat') disp('showing Triode-Sat Boundary - Hit any key to continue') pause %

38 ENGR-43_Lec-12a_FETs-1.pptx 38 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MATLAB Code-2 % then iD in triode region vDSt1 = linspace(0, vDSsat(1)); % V vDSt2 = linspace(0, vDSsat(2)) vDSt3 = linspace(0, vDSsat(3)) vDSt4 = linspace(0, vDSsat(4)) iDt1_mA = K*(2*(vGS(1)-Vto)*vDSt1-vDSt1.^2)/1000; % mA iDt2_mA = K*(2*(vGS(2)-Vto)*vDSt2-vDSt2.^2)/1000; % mA iDt3_mA = K*(2*(vGS(3)-Vto)*vDSt3-vDSt3.^2)/1000; % mA iDt4_mA = K*(2*(vGS(4)-Vto)*vDSt4-vDSt4.^2)/1000; % mA % % DeBug Command =>plot(vDSt1,iDt1_mA, vDSt4,iDt4_mA) % % use TwoPoint Plots in Sat iDsat1 =[iDsat_mA(1),iDsat_mA(1)] iDsat2 =[iDsat_mA(2),iDsat_mA(2)] iDsat3 =[iDsat_mA(3),iDsat_mA(3)] iDsat4 =[iDsat_mA(4),iDsat_mA(4)] vDSsat1 = [vDSsat(1), 10] vDSsat2 = [vDSsat(2), 10] vDSsat3 = [vDSsat(3), 10] vDSsat4 = [vDSsat(4), 10] %

39 ENGR-43_Lec-12a_FETs-1.pptx 39 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MATLAB Code-3 % % Now Concatenate to ocver Triode & Saturation Regions iD1 = [iDt1_mA,iDsat1] vDS1 = [vDSt1, vDSsat1] iD2 = [iDt2_mA,iDsat2] vDS2 = [vDSt2, vDSsat2] iD3 = [iDt3_mA,iDsat3] vDS3 = [vDSt3, vDSsat3] iD4 = [iDt4_mA,iDsat4] vDS4 = [vDSt4, vDSsat4] % % Finally Make Plot plot(vDSco, iDco,'b', vDS1, iD1,'c', vDS2, iD2,'g', vDS3, iD3,'m', vDS4, iD4,'r', 'LineWidth', 3),... grid, xlabel('vDS (Volts)'), ylabel('iD (mA)'), title('nMOSFET vi Curve - Ex 12.1'),... gtext('VGS

40 ENGR-43_Lec-12a_FETs-1.pptx 40 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis pMOSFET A pMOS FET is the Complement to the nMOS version. The channel is normally n-Type and a hole-populated conducting Channel is formed by applying a NEGATIVE v GS Basically the pMOS version looks like the nMOS FET with voltage-polarities inverted Channel pMOSFET Circuit Symbol

41 ENGR-43_Lec-12a_FETs-1.pptx 41 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis p & n MOSFET Comparison

42 ENGR-43_Lec-12a_FETs-1.pptx 42 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis All Done for Today 3 & 4 Connection nFET

43 ENGR-43_Lec-12a_FETs-1.pptx 43 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical & Mechanical Engineer Engineering 43 Appendix Diode vi Curves

44 ENGR-43_Lec-12a_FETs-1.pptx 44 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

45 ENGR-43_Lec-12a_FETs-1.pptx 45 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

46 ENGR-43_Lec-12a_FETs-1.pptx 46 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis


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