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FET Biasing 1. Introduction For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockleys equation.

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Presentation on theme: "FET Biasing 1. Introduction For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockleys equation."— Presentation transcript:

1 FET Biasing 1

2 Introduction For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockleys equation. For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockleys equation. Nonlinear functions results in curves as obtained for transfer characteristic of a JFET. Nonlinear functions results in curves as obtained for transfer characteristic of a JFET. Graphical approach will be used to examine the dc analysis for FET because it is most popularly used rather than mathematical approach Graphical approach will be used to examine the dc analysis for FET because it is most popularly used rather than mathematical approach The input of BJT and FET controlling variables are the current and the voltage levels respectively The input of BJT and FET controlling variables are the current and the voltage levels respectively 2

3 JFETs differ from BJTs: Nonlinear relationship between input (V GS ) and output (I D ) JFETs are voltage controlled devices, whereas BJTs are current controlled Introduction 3

4 Common FET Biasing Circuits JFET – Fixed – Bias – Self-Bias – Voltage-Divider Bias Depletion-Type MOSFET – Self-Bias – Voltage-Divider Bias Enhancement-Type MOSFET – Feedback Configuration – Voltage-Divider Bias Introduction 4

5 General Relationships For all FETs: For JFETs and Depletion-Type MOSFETs: For Enhancement-Type MOSFETs: 5

6 Fixed-Bias Configuration The configuration includes the ac levels Vi and Vo and the coupling capacitors. The configuration includes the ac levels Vi and Vo and the coupling capacitors. The resistor is present to ensure that Vi appears at the input to the FET amplifier for the AC analysis. The resistor is present to ensure that Vi appears at the input to the FET amplifier for the AC analysis. 6

7 Fixed-Bias Configuration For the DC analysis, For the DC analysis, Capacitors are open circuits Capacitors are open circuits and and The zero-volt drop across R G permits replacing R G by a short-circuit The zero-volt drop across R G permits replacing R G by a short-circuit 7

8 Fixed-Bias Configuration Investigating the input loop I G =0A, therefore I G =0A, therefore V RG =I G R G =0V V RG =I G R G =0V Applying KVL for the input loop, Applying KVL for the input loop, -V GG -V GS =0 V GG = -V GS It is called fixed-bias configuration due to V GG is a fixed power supply so V GS is fixed It is called fixed-bias configuration due to V GG is a fixed power supply so V GS is fixed The resulting current, The resulting current, 8

9 Investigating the graphical approach. Investigating the graphical approach. Using below tables, we Using below tables, we can draw the graph can draw the graph V GS IDIDIDID 0 I DSS 0.3V P I DSS /2 0.5 I DSS /4 VPVPVPVP0mA 9

10 The fixed level of V GS has been superimposed as a vertical line at The fixed level of V GS has been superimposed as a vertical line at At any point on the vertical line, the level of V G is -V GG --- the level of I D must simply be determined on this vertical line. At any point on the vertical line, the level of V G is -V GG --- the level of I D must simply be determined on this vertical line. The point where the two curves intersect is the common solution to the configuration – commonly referrers to as the quiescent or operating point. The point where the two curves intersect is the common solution to the configuration – commonly referrers to as the quiescent or operating point. The quiescent level of I D is determine by drawing a horizontal line from the Q-point to the vertical I D axis. The quiescent level of I D is determine by drawing a horizontal line from the Q-point to the vertical I D axis. 10

11 Output loop Output loop 11

12 Example Determine V GS Q, I D Q, V DS, V D, V G, V S Determine V GS Q, I D Q, V DS, V D, V G, V S 12

13 Exercise Determine I D Q, V GS Q, V DS, V D, V G and V S Determine I D Q, V GS Q, V DS, V D, V G and V S 13

14 Self Bias Configuration The self-bias configuration eliminates the need for two dc supplies. The self-bias configuration eliminates the need for two dc supplies. The controlling V GS is now determined by the voltage across the resistor R S The controlling V GS is now determined by the voltage across the resistor R S 14

15 For the indicated input loop: Mathematical approach: rearrange and solve. 15

16 Graphical approach Graphical approach Draw the device transfer characteristic Draw the device transfer characteristic Draw the network load line Draw the network load line Use to draw straight line. Use to draw straight line. First point, First point, Second point, any point from I D = 0 to I D = I DSS. Choose Second point, any point from I D = 0 to I D = I DSS. Choose the quiescent point obtained at the intersection of the straight line plot and the device characteristic curve. the quiescent point obtained at the intersection of the straight line plot and the device characteristic curve. The quiescent value for I D and V GS can then be determined and used to find the other quantities of interest. The quiescent value for I D and V GS can then be determined and used to find the other quantities of interest. 16

17 17

18 For output loop For output loop Apply KVL of output loop Apply KVL of output loop Use I D = I S Use I D = I S 18

19 19

20 Example Determine V GS Q, I D Q,V DS,V S,V G and V D. Determine V GS Q, I D Q,V DS,V S,V G and V D. 20

21 Example Determine V GS Q, I D Q, V D,V G,V S and V DS. Determine V GS Q, I D Q, V D,V G,V S and V DS. 21

22 Voltage-Divider Bias The arrangement is the same as BJT but the DC analysis is different The arrangement is the same as BJT but the DC analysis is different In BJT, I B provide link to input and output circuit, in FET V GS does the same In BJT, I B provide link to input and output circuit, in FET V GS does the same 22

23 Voltage-Divider Bias The source V DD was separated into two equivalent sources to permit a further separation of the input and output regions of the network. The source V DD was separated into two equivalent sources to permit a further separation of the input and output regions of the network. I G = 0A,Kirchoffs current law requires that I R1 = I R2 and the series equivalent circuit appearing to the left of the figure can be used to find the level of V G. I G = 0A,Kirchoffs current law requires that I R1 = I R2 and the series equivalent circuit appearing to the left of the figure can be used to find the level of V G. 23

24 Voltage-Divider Bias V G can be found using the voltage divider rule : V G can be found using the voltage divider rule : Using Kirchoffs Law on the input loop: Using Kirchoffs Law on the input loop: Rearranging and using ID =IS: Rearranging and using ID =IS: Again the Q point needs to be established by plotting a line that intersects the transfer curve. Again the Q point needs to be established by plotting a line that intersects the transfer curve. 24

25 Procedures for plotting 1. Plot the line: By plotting two points: V GS = V G, I D =0 and V GS = 0, I D = V G /R S 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3. Where the line intersects the transfer curve is the Q point for the circuit. 25

26 Once the quiescent values of I DQ and V GSQ are determined, the remaining network analysis can be found. Once the quiescent values of I DQ and V GSQ are determined, the remaining network analysis can be found. Output loop: Output loop: 26

27 Effect of increasing values of R S 27

28 Example Determine I D Q, V GS Q, V D, V S, V DS and V DG. Determine I D Q, V GS Q, V D, V S, V DS and V DG. 28

29 Example Determine I D Q, V GS Q, V DS, V D and V S Determine I D Q, V GS Q, V DS, V D and V S 29

30 Depletion-type MOSFET bias circuits are similar to JFETs. The only difference is that the depletion-Type MOSFETs can operate with positive values of V GS and with I D values that exceed I DSS. Depletion-Type MOSFETs 30

31 The DC Analysis Same as the FET calculations Same as the FET calculations Plotting the transfer characteristics of the device Plotting the transfer characteristics of the device Plotting the at a point that V GS exceeds the 0V or more positive values Plotting the at a point that V GS exceeds the 0V or more positive values Plotting point when V GS =0V and I D =0A Plotting point when V GS =0V and I D =0A The intersection between Shockley characteristics and linear characteristics defined the Q-point of the MOSFET The intersection between Shockley characteristics and linear characteristics defined the Q-point of the MOSFET The problem is that how long does the transfer characteristics have to be draw? The problem is that how long does the transfer characteristics have to be draw? We have to analyze the input loop parameter relationship. We have to analyze the input loop parameter relationship. As R S become smaller, the linear characteristics will be in narrow slope therefore needs to consider the extend of transfer characteristics for example of voltage divider MOSFET, As R S become smaller, the linear characteristics will be in narrow slope therefore needs to consider the extend of transfer characteristics for example of voltage divider MOSFET, The bigger values of V P the more positive values we should draw for the transfer characteristics The bigger values of V P the more positive values we should draw for the transfer characteristics Depletion-Type MOSFETs 31

32 Analyzing the MOSFET circuit for DC analysis How to analyze dc analysis for the shown network? How to analyze dc analysis for the shown network? It is a …. Type network It is a …. Type network Find V G or V GS Find V G or V GS Draw the linear characteristics Draw the linear characteristics Draw the transfer characteristics Draw the transfer characteristics Obtain V GSQ and I DQ from the graph intersection Obtain V GSQ and I DQ from the graph intersection 32

33 1. Plot line for V GS = V G, I D = 0 and I D = V G /R S, V GS = 0 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3. Where the line intersects the transfer curve is the Q-point. Use the I D at the Q-point to solve for the other variables in the voltage-divider bias circuit. These are the same calculations as used by a JFET circuit. 33

34 When R S change…the linear characteristics will change.. 1. Plot line for V GS = V G, I D = 0 and I D = V G /R S, V GS = 0 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3. Where the line intersects the transfer curve is the Q-point. Use the I D at the Q-point to solve for the other variables in the voltage-divider bias circuit. These are the same calculations as used by a JFET circuit. 34

35 The transfer characteristic for the enhancement-type MOSFET is very different from that of a simple JFET or the depletion-typeMOSFET. Enhancement-Type MOSFET 35

36 Transfer characteristic for E-MOSFET Transfer characteristic for E-MOSFETand 36

37 Feedback Biasing Arrangement I G =0A, therefore V RG = 0V Therefore: V DS = V GS Which makes 37

38 1. Plot the line using V GS = V DD, I D = 0 and I D = V DD / R D and V GS = 0 2.Plot the transfer curve using V GSTh, I D = 0 and V GS(on), I D(on) ; all given in the specification sheet. 3.Where the line and the transfer curve intersect is the Q-Point. 4.Using the value of I D at the Q-point, solve for the other variables in the bias circuit. Feedback Biasing Q-Point 38

39 DC analysis step for Feedback Biasing Enhancement type MOSFET Find k using the datasheet or specification given; Find k using the datasheet or specification given; ex: V GS(ON),V GS(TH) ex: V GS(ON),V GS(TH) Plot transfer characteristics using the formula Plot transfer characteristics using the formula I D =k(V GS – V T ) 2. Three point already defined that is I D(ON), V GS(ON) and V GS(TH) Plot a point that is slightly greater than V GS Plot a point that is slightly greater than V GS Plot the linear characteristics (network bias line) Plot the linear characteristics (network bias line) The intersection defines the Q-point The intersection defines the Q-point 39

40 Example Determine I D Q and V DS Q for network below Determine I D Q and V DS Q for network below 40

41 Again plot the line and the transfer curve to find the Q-point. Using the following equations: Input loop: Output loop: Voltage-Divider Biasing 41

42 1.Plot the line using V GS = V G = (R 2 V DD )/(R 1 + R 2 ), I D = 0 and I D = V G /R S and V GS = 0 2. Find k 3. Plot the transfer curve using V GSTh, I D = 0 and V GS(on), I D (on); all given in the specification sheet. 4. Where the line and the transfer curve intersect is the Q-Point. 5. Using the value of I D at the Q-point, solve for the other variables in the bias circuit. Voltage-Divider Bias Q-Point 42

43 Example Determine I D Q and V GS Q and V DS for network below Determine I D Q and V GS Q and V DS for network below 43

44 = =- - = - = -+)( = = - + =- )( + = = - )( = = 44

45 = - = = =- = - = - = + -= = - + ( ) = = - = =

46 Troubleshooting N-channel V GSQ will be 0V or negative if properly checked N-channel V GSQ will be 0V or negative if properly checked Level of V DS is ranging from 25%~75% of V DD. If 0V indicated, theres problem Level of V DS is ranging from 25%~75% of V DD. If 0V indicated, theres problem Check with the calculation between each terminal and ground. There must be a reading, R G will be excluded Check with the calculation between each terminal and ground. There must be a reading, R G will be excluded 46

47 For p-channel FETs the same calculations and graphs are used, except that the voltage polarities and current directions are the opposite. The graphs will be mirrors of the n-channel graphs. P-Channel FETs 47

48 Voltage-Controlled Resistor JFET Voltmeter Timer Network Fiber Optic Circuitry MOSFET Relay Driver Practical Applications 48

49 JFET Voltmeter 49

50 Advantages High Input impedance for isolation. High Input impedance for isolation. Amount of power drawn from circuit under test is very small, so no loading effect. Amount of power drawn from circuit under test is very small, so no loading effect. Very high sensitivity. Very high sensitivity. Amplifier gain allows measurement in the mV range. Amplifier gain allows measurement in the mV range. No damage due to overload because of amplifier saturation. No damage due to overload because of amplifier saturation. 50

51 Single MOSFET Relay Toggle Circuit 51


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