Presentation on theme: "Library Features Standard cells 9 tracks, 600 cells"— Presentation transcript:
1TSMC Libraries Advanced Technology Standard Cells Industry Standard I/Os
2Library Features Standard cells 9 tracks, 600 cells Multiple Vt, ECO cells, low power architecturesAll major EDA viewsGeneral purpose I/OsLatch-up characterized to 200 milliampsPad- and core-limited varieties availableESD characterized to 2kV/200V model (HBM/MM)
3TSMC Library Distribution and Support Developed and validated by TSMCDistributed by <Distributor>Standard cellsGeneral purpose digital I/O’sSupport provided by <Distributor>Hotline and AE service in the excellent tradition of <Distributor>Library updates and bug fixes are done by TSMCIf customized characterization or library elements are required, <Distributor> will direct those requests to TSMC
4Why is TSMC Creating Libraries? To create a comprehensive choice of industry-leading standard cell, I/O and memory libraries in the leading process technologies, complementing internal offerings with 3rd party partner offeringsTo productize the cells used in wafer process development, and test them in real-world EDA flows, to provide process-tuned design architectures that fully utilize TSMC’s silicon technologyTo set the industry standard for quality with TSMC 9000 compliant productsTo fulfill increasing demand for segment-targeted building blocksTo utilize distribution partners with strong, global field organizations to serve designers throughout the design cycle
5Who is Using TSMC Libraries? I/Os: In production, in hundreds of productsStandard cells: Rapid customer adoption incommunications segmentconsumer segmentAll geographic regionsAmericasJapanEuropeAsiaAll leading processes0.15 mm0.13 mm90 nmThe advanced technology libraries for TSMC design
6TSMC Standard Cell Libraries The advanced technology libraries for TSMC design
7TSMC Standard Cell Roadmap 0.13umCL013DatapathCL013GHvt-Nvt-LvtCL013LV (OD)Hvt-NvtCL013LPNvt-Lvt90nmCLN90GHvt-Nvt-LvtCLN90LPUHvt-Hvt-NvtCLN90GBack-biasCLN90GODHvt-Nvt-LvtCLN90GMulti-VddCLN90GECO CellsCLN90DatapathQ Q Q Q QLeft edge of each box represents first release schedule, when design kits are ready
8Advanced Technology Library Features Ready for marketPowerTimingDFM
9Advanced Technology Library Features Ready for marketCompetitive cell density, 9 track architecturePre-tested with advanced design flowsCommercial and industry specs availableTested in siliconPowerTimingDFM
10Advanced Technology Library Features Ready for marketPowerDecoupling capacitors available in filler cellsComprehensive libraries with standard, overdrive and multi-Vt cellsOverdrive 0.13mm LVMulti-Vt all 0.13mm, all 90nmSignal current characterization methodology for electromigration (EM) and wide wire routingAdded corners for advanced leakage characterization (90nm, 0.13mm)TimingDFMNew in Q4’03 !!
11Advanced Technology Library Features Ready for marketPowerTimingMost popular timing featuresIndustry-standard slew rate transition modelSetup/hold time uses “CLK-to-Q 10% push out” constraintDFMNew in Q4’03 !!
12Advanced Technology Library Features Ready for marketPowerTimingDFMBuilt-in antenna diodes in clock buffer cellsAdvanced TSMC-tuned DFM featuresunidirectional gate polycontact/metal overlap DFM guidelines usedCompliant with advanced TSMC “LOD” Spice model (90nm, Q4’03)New in Q4’03 !!
13Multiple Threshold (Multi-Vt) for Both Power and Performance Best of both worldsshorter delay (Low-Vt)lower power (Std- and Hi-Vt)Interchangeable footprints:Freely swap cells from Hi-, Std-, or Low-VtVertical and horizontal abutment allowedFully tested in TSMC Reference Flow1Unique to TSMC1Unique to TSMCThe advanced technology libraries for TSMC design
14New for Power Efficiency The World’s Most Advanced Power Architectures Back bias cellsStandby mode in addition to normal modeExponential decrease in leakageMultiple VddBlock-based Vdd assignmentLower switching currentPre-release in Q2’041Unique to TSMCThe advanced technology libraries for TSMC design
15The advanced technology libraries for TSMC design ECO Change for Design Flexibility Advanced technology for faster time-to-marketAllows respin of chip with simple logic patchesLogic elements to patch a circuit, in filler cell footprint30 different cells availableModify contact, M1 (and above) to patch the logic for ECODecoupling caps may be placed in unused filler cellsPre-release in Q2’04Filler CellDe-cap CellECO Cell1Unique to TSMCThe advanced technology libraries for TSMC design
16Std Cell Design Kit Deliverables New in Q4’03 !!
17Standard Cell Categories Cell Family0.15um0.13um90nmDrive Strength(AND/NAND) / (OR/NOR) / (XOR/XNOR)3 each3 each3 each5 / 6 / 4 eachBUFFER / 3-STATE BUFFER: w/ & w/o enable/inverter1 each1 each1 each11 eachAOI / OAI / AO / OA / MAO / MOAI12 each39394 eachADDER: half/full adder1 each333/2 eachMUX: w & w/o inverted output3 each664 eachCLK BUFFER / Inverted CLK BUFFER / Gated CLK LATCH1 each1 each1 each11 / 11 / 10 eachDFF: pos-edge, neg-edge, async/sync R/S, w/o R/S1515153 eachENABLE DFF; async/sync R, w/o R flip-flop6663 eachSCAN DFF: all version of scan flip-flop2123233 eachLATCH: active high/low enable, async R/S8883 eachINV/NAND/AND/MUX/XOR (balanced rise/fall)1 each554 eachDELAY/TIE-HIGH/TIE-LOW cell1 each444 / 1 / 1(7/1/1)ANTENNA/DECOUPLING cell2, 777N/ATotal Cell Number514600*600*New in Q4’03 !!*90nm and 0.13um libraries include over 30 datapath cells
18TSMC Std Cell Library Comparison NEWNEWNEWNEWNEW* All libraries use 9-track height cells; raw gates use ND2D1 area as 1 gate* OD, HVT and LVT: Over Drive, High Vt and Low Vt nodes* Leakage/Power/Performance data are based on 2-input NAND gate (ND2D1) with 3X standard loads in nominal conditionsNEWAdded in 2H03
19New for 0.15 mm 8 track architecture High density Tuned for consumer applicationsQ4’03New in Q4’03 !!
20Standard Cell Timing Characterization Conditions Some processes such as Overdrive have different conditions; check with TSMC
21TSMC Standard Cell Characterization Sets the industry standard Extensive Characterization:Input pin capacitancePropagation Delay, Transition TimeSetup/Hold TimeRecovery/Removal Time/Minimum Pulse WidthLeakage, Internal PowerHigh Accuracy:7 X 7 Lookup Table for timing & power calculationAdvanced Power Parameters:Pin-to-Pin Power Table supportedState-dependent delay, internal power (selected cells)Input pin state-dependent leakageCell output Irms characterized for EM at 500MHz1Unique to TSMC
22Widespread Adoption, Working Silicon Customer #1: networkTaped out MPW in February 2003, silicon functionalCustomer #2: programmable logicTaped out MPW in June 2003, silicon functionalCustomer #3: major IDMMultiple tape-outs plannedCustomer #1: handsetTaped out 0.13G multi-Vt in April 2003, silicon functionalCustomer #2: wirelessTaped out 0.13G multi-Vt in July 2003 , silicon functionalCustomer #3: computerWill tape out 0.13LV-OD in Q4/2003Customer #4: storageWill tape out 0.13G in Q4/2003Customer #1: communicationIn pilot production now (0.15G)Customer #2: consumerWill tape out in Q4/2003 (0.15G)Customer #3: consumerWill tape out in Q4/2003 (0.15LV)90 nm0.13 mm0.15 mm
23TSMC 9000 Validation Status Standard Cell LibraryTSMC 9000 Validation StatusLevel 10.15 mm All0.13 mm All90 nm AllLevel 30.15 mm AllLevel 50.15 mm GLevel 1 All cells reviewed Design kit completeLevel 3 Test chip validationSilicon report availableLevel 5 ProductionNew in Q4’03 !!
24N90 Success Story – Processor Core Design specification:Process: TSMC 90nm logic 1P6M Low-KGate count: 1M gatesMemory: 140KB (20 memory instances)Chip size: 3x3 mm squareTarget Frequency: 350+MHzLibrary & Flow:TSMC 90um multi-Vt Std. Cell libraryTSMC digital I/O cellsMulti-Vt power/performance optimizationTSMC Reference Flow 4.0Hierarchical partition and physical P&R implementationSilicon Status: In progress
25CL013 Success Story – Cellular Phone Chip First time silicon success! Design specification:Process: TSMC 0.13 mm 1.2V/3.3V 1P6M FSGGate count: M gatesMemory: 485KBChip size: 9x9 mm squareFrequency Target: MHzPackage: pins BGALibrary & Flow:TSMC 0.13 mm multi-Vt Std. cell libraryTSMC digital & analog I/O cellsMulti-Vt script design methodologyPrecise leakage cell modeling for leakage and speed trade-offFirst time silicon success!
26The advanced technology libraries for TSMC design SummaryAdvanced DFM featuresAdvanced power featuresAdvanced ECO flexibilityMost extensive characterizationFlow proven and silicon validatedRapid market adoptionThe advanced technology libraries for TSMC design
27TSMC Standard I/O Libraries The most widely used I/O libraries for TSMC design
28TSMC Std I/O Portfolio Summary NEWNEWNEWNEW* tol = tolerantNEWAdded in 2H03
29CL013 I/O Library Features Process: mm logic salicide, from 4 to 8 metalsVoltage combinations* tol = tolerantCells:123 I/O cells2 corner cells6 bond pads7 filler padsBonding type: staggered or linearBody cell width/height:35mm x 246mm (tpz013g2/g3/lg2)35mm x 276mm (tpz013lg3)60mm x 150mm (tpd013lpn3)
30CLN90 I/O Library Features Process: 90 nm logic salicide, from 5 to 9 metal layersVoltage combinationsCells:18 I/O cells, programmable to over 75 configurations1 corner cell6 bond pads7 filler padsBonding type: linearBody cell width/height:35mm x 210mm
31CL015 I/O Library Features Process: mm logic salicide, from 4 to 7 metalsVoltage combinations* tol = tolerantCells:123 I/O cells1 corner cell2 bond pads7 filler padsBonding type: staggeredBody cell width/height:40mm x 230mm (tpz015lg/g)
32TSMC 9000 Validation Status I/O LibraryTSMC 9000 Validation StatusLevel 10.15 mm All0.13 mm All90 nm AllLevel 30.13 mm GLevel 50.13 mm Formal status underwayProduction of 2.5V + 3.3V : over 20,000 wafers!Level 1 All cells reviewed Design kit completeLevel 3 Test chip validationSilicon report availableLevel 5 Production
33The most widely used I/O libraries for TSMC design SummaryAvailable for production in TSMC processesUsed in hundreds of products, tens of thousands of wafersPackaged by all leading backend housesThe most widely used I/O libraries for TSMC design