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© 2011 IBM Corporation Placement: Hot or Not Chuck Alpert Design Productivity Group Austin Research Laboratory.

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Presentation on theme: "© 2011 IBM Corporation Placement: Hot or Not Chuck Alpert Design Productivity Group Austin Research Laboratory."— Presentation transcript:

1 © 2011 IBM Corporation Placement: Hot or Not Chuck Alpert Design Productivity Group Austin Research Laboratory

2 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation The State of Placement Placement is an old problem Rajeev: Today, the EDA academic community is not producing a lot of new ideas. Yes, at one time they did, but not today. Lou Scheffer : place-and-route is in reasonable shape 2

3 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Placement Trends (my guess, not scientific) 3 Chip gate count: 21 M Largest Block: 1.5 M Chip gate count: 76 M Largest Block: 3.7 M

4 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Placement is Hot Design sizes are exploding Designers are embracing automation like never before Secondary factors (power, area) become differentiating Wirelength is no longer primary –Congestion –Timing –Power –Clock-friendly 4

5 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Generic Design Flow 5 From Cadence

6 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 6 Vt Optimization? Swap to lower vt

7 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 7 Gate Sizing or Repowering b f e c a d b f e c a d

8 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 8 Buffering and Layer Assignment

9 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 9 Inverter Absorption / Decomposition b f e c a d b f e a g

10 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 10 Composition / Decomposition nd2 A nd2 C nd2 B D Out x y z w nd2 C D y z x w Out AOI Courtesy: Louise Trevillian, founder of Logic Synthesis

11 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Example Timing Closure Optimization 11 While 500 most critical nets still optimizable Gate sizing and vt Optimization Buffering on sub-tree Buffering on entire tree Congestion-aware layer assignment Suite of logic transforms For remaining critical nets Gate sizing and vt Optimization Buffering, layer assignment on sub-tree Critical Path Optimization Compression Optimization

12 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation What Timing-Driven Placement Means 12 SynthesisTraditional PlacementOptimizationSet Net WeightsTiming-driven PlacementOptimization Weight all nets? If not, what percent? What weight range? What netlist state for timing-driven placement?

13 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 13 Over Weight Can Destroy Congestion Initial After Timing-driven Placement Optimization Placement

14 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Dont Put Timing into Placement! 14 Timing Placement Timing-driven Placement Flow Placement Constraint Generation Timing Incremental Placement Easy Constraints

15 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Example Incremental Timing-Driven Placement 15 Initial Final

16 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Techniques Required for Timing-Driven Placement Identification of easy constraints Incremental Placement –Shorten critical paths without hurting other paths –Fast, incremental wirelength recovery –Congestion-preserving detailed placement (dont pack!) –Getting pipeline latches right Meaningful timing model Interleave optimization (e.g., layer assignment) 16

17 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 17 Pipeline Latch Placement

18 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 18 Pipeline Latch Placement

19 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 19 Interference From Other Logic Logic

20 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Power-Aware Placement 20 Switching Factor #nets

21 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Congestion Still Huge Problem Contests focus on congestion-driven placement Also need for incremental congestion repair Fast, accurate congestion modeling is key 21 Placement APlacement B Router 1 Placement APlacement B Router 2

22 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Placement Density Reasonable First Order 22

23 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 23 Local Congestion Effects (Pin Density) Before Spreading After Spreading

24 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 24 Handling Movebounds

25 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation

26 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Move Bound Challenges 26 Dont increase runtime High density / low density Inclusive or exclusive OverlappingSoft or absolute Different shapes Support high quantity

27 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Datapath Placement 27 LEGAL HPWL = LEGAL HPWL = LEGAL HPWL = Base RunSoft AlignmentForced Alignment net1 ( Fixed pins net1 Courtesy: Sam Ward

28 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 28 July 26, 2012 Latch Huddling: Good For Clock Skew and Power

29 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Why Huddling is Good for Clocks 29 More Clock Wire Less Clock Wire

30 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation 30 All Object Movement (Before and After Huddling) Global Huddling Placement Incremental Huddling Placement movement (in tracks)

31 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Global Clock Trees 31 Challenge, can we separate three trees to prevent routing overlap?

32 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Proposed Placement Framework Keep placement as a stand alone optimization Enrich it to handle constraints Add constraint generation step to guide placement –Move bounds –Power Switching factors –Tightness of latch huddles –Clock domain separation –Use of hierarchical name space –Alignment of datapath 32

33 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Proposed Placement Flow 33 Placement (Global or Incremental) Constraint Generation Timing Analysis Power Analysis Congestion Analysis Clock Analysis Pre-Placement Constraints

34 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Do We Need to Write a Placer from Scratch? 34 Clustering Clustered Global Flat Global Density Spreading Congestion Mitigation Fast Congestion Analysis Congestion-aware Detailed Placement Pin-Density Spreading Power Reduction

35 Design Productivity Group, Austin Research Laboratory © 2011 IBM Corporation Chasing the Hot Topics 35 Instead of trying to predict the next important problem Just ask (a designer)


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