1.  1999 Arizona Board of Regents for The University of Arizona
Semiconductor Manufacturing Technology: Semiconductor Manufacturing Processes
Conrad T. Sorenson
Praxair, Inc.
 1999 Arizona Board of Regents for The University of Arizona
Semiconductor Manufacturing Technology
It has been fifty years since the invention of the transistor. The technology behind this topic cannot be addressed adequately in a single presentation, but has been separated into four modules:
Module 1: Basic Principles
Module 2: Transistor Design and Manufacturing Overview
Module 3: Semiconductor Manufacturing Processes
Module 4: Semiconductor Economics
In this third module, we will review the key semiconductor processes, materials and equipment used to fabricate devices, and discuss process conditions and chemistry.
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 1

2. Semiconductor Manufacturing Processes
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Design
Wafer Preparation
Front-end Processes
Photolithography
Etch
Cleaning
Thin Films
Ion Implantation
Planarization
Test and Assembly
Semiconductor Manufacturing Processes
The process of building a chip’s circuitry involves several different basic steps that are repeated many times. These steps are:
Design
Wafer Preparation
Front-end Processes
Photolithography
Etch
Cleaning
Thin Films
Ion Implantation
Planarization
Test and Assembly
I will describe each process following the typical sequence for making leading-edge semiconductor devices.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 2

3. Design Establish Design Rules Circuit Element Design
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Establish Design Rules
Circuit Element Design
Interconnect Routing
Device Simulation
Pattern Preparation
Design
The first operation is the design of the chip. When tens of millions of transistors are to be built on a square of silicon about the size of a child’s fingernail, the placing and interconnections of the transistors must be meticulously worked out. Each transistor must be designed for its intended function, and groups of transistors are combined to create circuit elements such as inverters, adders and decoders. The designer must also take into account the intended purpose of the chip. A processor chip carries out instructions in a computer, and a memory chip stores data. The two types of chips differ somewhat in structure. Because of the complexity of today’s chips, the design work is done by computer, although engineers often print out an enlarged diagram of a chip’s structure to examine it in detail.
The basic steps of Design are:
Designing the transistor architecture and establishing design rules,
Designing basic circuit elements that can be used as building blocks for more complex circuits,
Routing the 10 kilometers of wiring so that the signal reaches the desired circuit elements correctly and without reaching undesired circuit elements.
Simulating the complex circuit so that undesired properties can be eliminated, and
Preparing the pattern for lithography.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 3

4. Pattern Preparation Reticle Chrome Pattern Quartz Substrate Pellicle
Semiconductor devices are made up of as many as 50 individual layers of silicon, polysilicon, silicon dioxide, metal and silicides. The pattern for each layer is contained on a mask called a reticle. A reticle is an optically clear quartz substrate with a chrome pattern. Reticles are typically 10 times larger than the actual size of the pattern they will produce. The group of reticles that make up all the layers of a semiconductor device is called a device series. To keep the surface of the reticle clean, a thin plastic sheet called a pellicle is mounted a short distance away from the surface of the reticle. This allows the wafer to be cleaned without directly contacting the chrome mask surface, but also insures that any microscopic dust that settles on the reticle will be out of focus during exposure and not create defects.
Semiconductor device manufacturers design the pattern for each layer using CAD software, then prepare a chrome coated reticle blank and apply a layer of photoresist. The CAD pattern is transferred to the reticle using an electron-beam writer. The reticles are developed, etched (removing the chrome mask where there is no masking pattern), stripped of masking photoresist, then inspected.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 4

5. Wafer Preparation Polysilicon Refining Crystal Pulling
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Polysilicon Refining
Crystal Pulling
Wafer Slicing & Polishing
Epitaxial Silicon Deposition
Wafer Preparation
The base material for building an integrated circuit is a silicon crystal. Silicon, the second most abundant element on the earth after oxygen, is the principal ingredient of beach sand. Silicon is a natural semiconductor, which means that it can be altered to be either an insulator or conductor.
To make wafers from sand, the silicon must be refined and purified. The refined silicon is melted, trace amounts of impurities are added, then crystallized to form boules. Silicon boules are sliced into wafers and polished. A layer of epitaxial silicon (epi) is then deposited onto the polished silicon wafers.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 5

6. Polysilicon Refining Chemical Reactions
Silicon Refining: SiO2 + 2 C  Si + 2 CO
Silicon Purification: Si + 3 HCl  HSiCl3 + H2
Silicon Deposition: HSiCl3 + H2  Si + 3 HCl
Reactants H2
Silicon Intermediates
H2SiCl2
HSiCl3
Polysilicon Refining
To make a silicon wafer, raw silicon is refined from quartz rock by reacting it with carbon to form small, randomly oriented crystals of pure silicon, called polysilicon.
Raw silicon is reacted with hydrochloric acid to form trichlorsilane or TCS. TCS is mixed with hydrogen gas in a reaction furnace to form polycrystalline silicon which is allowed to grow on the surface of heated tantalum wicks.
The polycrystalline silicon is refined by dissolving the tantalum wicks in hydrofluoric acid and fused to produce polysilicon ingots.
Because polycrystalline silicon, also known as polysilicon, has randomly oriented crystals, it does not have the electrical characteristics necessary to fabricate semiconductor devices. Polysilicon must first be transformed into single crystal silicon using a process called Crystal Pulling.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 6

7. Crystal Pulling Process Conditions Flow Rate: 20 to 50 liters/min
Quartz Tube
Rotating Chuck
Seed Crystal
Growing Crystal
(boule)
RF or Resistance
Heating Coils
Molten Silicon
(Melt)
Crucible
Process Conditions
Flow Rate: 20 to 50 liters/min
Time: 18 to 24 hours
Temperature: >1,300 degrees C
Pressure: 20 Torr
Materials
Polysilicon Nodules *
Ar * H2
Silicon Crystal Growing
The most commonly used technique for silicon crystal growing is the Czochralski process where a silicon seed is slowly drawn from a crucible of molten silicon to produce a cylindrical ingot 100 to 300 mm in diameter and up to a meter in length. Crushed, high-purity polycrystalline silicon is doped with elements like arsenic, boron, phosphorous or antimony and melted at a temperature greater than 1300° C in a quartz crucible surrounded by an inert gas atmosphere of high-purity argon. The melt is cooled to a precise temperature, then a “seed” of single crystal silicon is placed into the melt and slowly rotated as it is “pulled” out. The surface tension between the seed and the molten silicon causes a small amount of the liquid to rise with the seed and cool into a single crystalline ingot with the same orientation as the seed. The ingot diameter is determined by controlling temperature and extraction speed. To minimize contamination of the silicon, the process takes place in an inert gas atmosphere at a pressure of 20 Torr.
Crystal pullers are installed on large concrete foundations (sometimes as large as an 8 foot cube) to control vibration, allow proper crystal orientation, and prevent defects.
Most ingots produced today are 200mm (8") in diameter, but silicon suppliers are switching to ingots that are 300mm (12") in diameter.
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 7

8. Wafer Slicing & Polishing
silicon wafer
p+ silicon substrate
Wafer Slicing & Polishing
Ingot Characterization
Single crystal silicon ingots are characterized by the orientation of their silicon crystals. Before the ingot is cut into wafers, the orientation of the crystal is marked by grinding a “flat” or “notch” along the silicon ingot.
Wafer Slicing
After characterization, wafer manufacturers slice the ingot into individual wafers with a precision thin-bladed saw designed to minimize waste (called “kerf”) but rigid enough to cut flatly.
Wafer Polishing
Wafers are typically polished to a high degree of flatness on one side. However, 300 mm wafers may be polished on both sides to improve photolithography resolution.
The silicon ingot is sliced into individual wafers, polished, and cleaned.
3/15/98
PRAX01C.PPT Rev. 1.0
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 8

9. Epitaxial Silicon Deposition
silicon wafer
p- silicon epi layer
p+ silicon substrate
Gas
Input
Susceptor
Lamp
Module
Chemical Reactions
Silicon Deposition: HSiCl3 + H2  Si + 3 HCl
Process Conditions
Flow Rates: 5 to 50 liters/min
Temperature: 900 to 1,100 degrees C.
Pressure: 100 Torr to Atmospheric
Quartz
Lamps
Wafers
Epitaxial Silicon Deposition
Silicon manufacturers use a process called epitaxial silicon growth to grow a layer of single crystal silicon from vapor onto a single crystal silicon substrate at high temperatures.
EPI layers are important for assuring device isolation and avoiding junction leakage in CMOS devices. The technology is moving from batch to single wafer processing in order to provide better process control and to achieve lower cost of ownership. A high temperature in-situ wafer pre-clean in HCl assures an oxide-free substrate. The epitaxial deposition uses a chlorinated silane reacting with hydrogen at temperatures of 900 to 1100° C. A precisely tailored dopant profile can be obtained by adding arsine, diborane, or phosphine in carefully controlled doses. Among the challenges in the technology is lowering the deposition temperature to below 900° C for defect reduction. This will require reducing contaminants, such as moisture or oxygen, in the reactor and finding new chemistries to increase the deposition rate.
In the future more wafers will have an epitaxy layer to improve silicon performance. Starting at 0.18 m, DRAM manufacturers are likely to use epitaxy. This will roughly double the percentage of wafers processed with epitaxy.
Dopants
AsH3
B2H6
PH3
Etchant
HCl
Carriers Ar
H2 * N2
Silicon Sources
SiH4
H2SiCl2
HSiCl3 *
SiCl4 *
Exhaust
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 9

10. Front-End Processes Thermal Oxidation Silicon Nitride Deposition
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Thermal Oxidation
Silicon Nitride Deposition
Low Pressure Chemical Vapor Deposition (LPCVD)
Polysilicon Deposition
Annealing
Front-End Processes
The Front-End of the line, often referred to as FEOL, describes the processes used to fabricate device structures from the starting silicon material through the construction of complete transistor structures. FEOL processes include:
1. Thermal Oxidation of silicon,
2. Low Pressure Chemical Vapor Deposition (LPCVD) of silicon nitride,
3. Low Pressure Chemical Vapor Deposition (LPCVD) of polysilicon, and
4. Annealing.
Due to the shallow junctions required for 0.18 m devices, the total amount of time a wafer can spend at high temperature (called the “thermal budget”) will be reduced. Even though processing will shift to less efficient single wafer rapid thermal processes because of thermal budget limitations and oxide thickness reduction, gas usage for these processes is expected to decline slightly. Due to a wafer technology shift towards ion implantation, the use of large cylinder dopant mixtures has been reduced.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 10

11. Front-End Processes Chemical Reactions
Exhaust Via
Vacuum Pumps
and Scrubber
3 Zone
Temperature
Control
Gas Inlet
Vertical LPCVD Furnace
Quartz Tube
Chemical Reactions
Thermal Oxidation: Si + O2  SiO2
Nitride Deposition: 3 SiH4 + 4 NH3  Si3N H2
Polysilicon Deposition: SiH4  Si + 2 H2
Process Conditions (Silicon Nitride LPCVD)
Flow Rates: sccm
Temperature: 600 degrees C.
Pressure: 100 mTorr
Front-End Processes
Thermal oxidation, silicon nitride deposition, polysilicon deposition and annealing operations are included in the front-end of the line processes.
Thermal Oxidation
The thermal oxidation of silicon uses oxygen in high temperature furnaces at atmospheric pressures. Furnace temperatures are in excess of 1,100° C and the process can take as log as 24 hours for thick oxides.
Polysilicon Deposition
Performed in Low Pressure (LP) CVD reactors, amorphous and poly silicon are thermally deposited from silane. The technology has migrated from horizontal furnaces to vertical furnaces to provide improved film uniformity, reduce particulate contamination, and improve grain structure uniformity, leading to better consistency in etch and conductance.
Silicon Nitride Deposition
Silicon nitride is deposited in LPCVD furnaces similar to those used for polysilicon deposition.
Annealing
Annealing is required to recrystallize the silicon after implantation and to activate new ionic bonds, typically done at high temperatures and atmospheric pressures.
Oxidation Ar N2
H2O
Cl2 H2
HCl *
O2 *
Dichloroethene *
Polysilicon H2 N2
SiH4 *
AsH3
B2H6
PH3
Nitride
NH3 *
H2SiCl2 * N2
SiH4 *
SiCl4
Annealing Ar He H2 N2
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 11

12. Photolithography Photoresist Coating Processes Exposure Processes
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Photoresist Coating Processes
Exposure Processes
Photolithography
The image of the circuit pattern is transferred to the wafer in a process known as photolithography. Wafers are first coated with a thin emulsion of photo-active organic material, called photoresist. The pattern of the device is very intricate and must be positioned accurately. This pattern is then projected onto the wafer using UV light. The resulting image is developed and inspected.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 12

13. Photoresist Coating Processes
field oxide
p- epi
p+ substrate
Photoresists
Negative Photoresist *
Positive Photoresist *
Other Ancillary Materials (Liquids)
Edge Bead Removers *
Anti-Reflective Coatings *
Adhesion Promoters/Primers (HMDS) *
Rinsers/Thinners/Corrosion Inhibitors *
Contrast Enhancement Materials *
Developers
TMAH *
Specialty Developers *
Inert Gases Ar N2
Photoresist Coating Processes
Photoresist or resist is a photo-sensitive material applied to the wafer in a liquid state in small quantities. The wafer is spun at 3000 rpm which spreads the “puddle” into a uniform layer typically around 2 µm thick.
Most semiconductor processes today use a positive resist where exposed portions are removed leaving a “positive” image of the mask pattern on the surface of the wafer.
Photoresists are specially formulated to trade-off sensitivity to short-wavelength light and chemical erosion resistance during etch processes. Photoresists must also have very low metal content.
There are many specialty chemicals used in the photolithography process including materials that promote adhesion of the photoresist to the silicon surface, materials that remove the bead of photoresist that forms at the edge of the wafer during spin application and materials that enhance the photosensitivity of the resist, inhibit corrosion, or thin the photoresist.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 13

14. Exposure Processes Expose Inert Gases Kr + F2 (gas) * N2
p- epi
p+ substrate
field oxide
photoresist
Expose
Kr + F2 (gas) *
Inert Gases N2
Exposure Processes
The image of the chip is projected through a mask and exposes a photo-active emulsion. Semiconductor device manufacturers expose wafers using a tool called a stepper. A stepper exposes a photoresist coated wafer to single wavelength UV light passing through a reticle which contains the image of a single device layer. The term “stepper” comes from the “step-and-repeat” action of moving the wafer on its x and y axes to align the reticle with each individual device position.
UV light is used because modern semiconductor device features are so small that the actual wavelength of the exposing light is a limiting factor. UV has a shorter wavelength (less than 500 nm) than visible light which allows the creation of smaller features. Typical wavelengths used are 436 nm (called G-Line), 405 nm (H-line), 365 nm (I-line) and 248 nm (called Deep UV). Today's semiconductors have features as small as 0.18 µm which require the use of single-wavelength Deep UV light sources, typically Eximer lasers using fluorine and noble gas mixtures. Semiconductor manufacturers are experimenting with 193 nm UV and also with X-ray (which has an even shorter wavelength).
Steppers are extremely high-precision devices and can cost upwards of $5 million each and are very sensitive to vibration and temperature variation. A typical stepper will print a single process layer on about 12 wafers per hour.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 14

15. Ion Implantation Well Implants Channel Implants Source/Drain Implants
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Well Implants
Channel Implants
Source/Drain Implants
Ion Implantation
Ion Implantation is different from other semiconductor processes because it does not create a new layer on the wafer. Instead, ion implantation changes the electrical characteristics of precise areas within an existing layer on the wafer.
Ion implanters, as shown in the next slide, are used...
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 15

16. Ion Implantation Process Conditions Flow Rate: 5 sccm
Focus
Neutral beam and
beam path gated
Beam trap and
gate plate
Wafer in wafer
process chamber
X - axis
scanner
Y - axis
Neutral beam trap
and beam gate
junction depth
Process Conditions
Flow Rate: 5 sccm
Pressure: Torr
Accelerating Voltage: 5 to 200 keV
180 kV
Resolving
Aperture
Ion Source
Equipment Ground
Acceleration Tube
90° Analyzing Magnet
Terminal Ground
20 kV
Gases Ar
AsH3
B11F3 * He N2
PH3
SiH4
SiF4
GeH4
Solids Ga In Sb
Liquids
Al(CH3)3
Ion Implantation
... to create shallow junctions, graded wells, deep wells, and to tailor polysilicon resistivity. The technology employs dopant gases or solids which serve as the source of phosphorous, boron, arsenic, etc. These materials are ionized and accelerated to the appropriate implant energy which is typically 5 to 200 keV. The ion beam is mass selected, focused, and scanned across the target wafers. Using sophisticated models as a guide, ion implant is coupled with controlled anneals to deliver precise dopant profiles. The current technology challenge is very low energy ion implants, which are used to make the shallow junctions ( 0.2 m) required in advanced technologies.
An ion implanter uses a high-current accelerator tube and steering and focusing magnets to bombard the surface of the wafer with ions of a particular dopant. These dopant ions are implanted into the top layer of the wafer just below the surface, changing the conductivity of a precise region. To create an insulating, or p-type, region an acceptor ion such as boron, gallium or indium is implanted. To create a conducting, or n-type, region a donor ion such as antimony, arsenic, phosphorus or bismuth is implanted.
Implanters are generally classified as high-current (a beam current higher than 3 milliamp), medium-current (less than 3 milliamp), or high energy implant, which can deposit triply-charged ions at up to 3 million eV.
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 16

17. Etch Conductor Etch Poly Etch and Silicon Trench Etch Metal Etch
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Conductor Etch
Poly Etch and Silicon Trench Etch
Metal Etch
Dielectric Etch
Etch
The semiconductor industry typically employs a technique called plasma etching to precisely transfer micro-images printed in photoresist into semiconductor process films. This is done by placing wafers into a vacuum chamber which is filled with an etch gas. A strong Radio Frequency or RF electromagnetic field is applied to the wafer. The RF field tears the molecules of etch gas apart into chemically reactive ions. The charged ions are accelerated toward the wafer surface by the electromagnetic field and form a microscopic chemical and physical “sandblasting” action which removes the exposed material.
Plasma etching selectively removes portions of semiconductor layers to leave microstructures on a device. The process must precisely eliminate the material left exposed by the photoresist pattern and avoid undercutting the sides of the remaining circuit elements.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 17

18. Conductor Etch Chemical Reactions
Chambers
Cluster Tool
Configuration
Transfer
Chamber
Loadlock
Wafers
Chemical Reactions
Silicon Etch: Si + 4 HBr  SiBr4 + 2 H2
Aluminum Etch: Al + 2 Cl2  AlCl4
Process Conditions
Flow Rates: 100 to 300 sccm
Pressure: 10 to 500 mTorr
RF Power: 50 to 100 Watts
RIE Chamber
Transfer
Chamber
Gas Inlet
Exhaust
RF Power
Wafer
Conductor Etch
Poly Etch and Silicon Trench Etch
Precise silicon etching is used to create shallow trenches for isolation, deep trenches for storage, and to pattern poly silicon. Current technology utilizes RF plasma sources at relatively high pressures of 500 mTorr. In order to achieve sub-half micron silicon etching, high density plasmas operated at 10 mTorr in single wafer tools are employed. With low pressure, a long mean free path of reactive ions assures a high degree of ion sputtering and highly anisotropic etching. The silicon etch gas mixture, utilizing both chlorine and hydrogen bromide, needs to be precisely controlled to achieve vertical sidewalls. For the case of poly etch, this chemistry also provides good selectivity to gate oxide.
Metal Etch
The key to interconnect technology is metal etching which provides precise image transfer from resist images into Al/Cu alloys, stopping on titanium nitride, or a doped or undoped oxide. The preferred chemistry is BCl3 and Cl2, which etched the metal with vertical metal sidewalls. And at sub-0.5 micron dimensions, the technology has moved toward single wafer high density plasma processes. These high density plasmas operate at about 10 mTorr. Metal etch processes are expected to become obsolete as the industry shifts to copper metalization.
Polysilicon Etches
HBr *
C2F6
SF6 *
NF3 * O2
Aluminum Etches
BCl3 *
Cl2
Diluents Ar He N2
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 18

19. Dielectric Etch Chemical Reactions
Contact locations
Etch
Chambers
Cluster Tool
Configuration
Transfer
Chamber
Loadlock
Wafers
Chemical Reactions
Oxide Etch: SiO2 + C2F6  SiF4 + CO2 + CF4 + 2 CO
Process Conditions
Flow Rates: 10 to 300 sccm
Pressure: 5 to 10 mTorr
RF Power: 100 to 200 Watts
RIE Chamber
Transfer
Chamber
Gas Inlet
Exhaust
RF Power
Wafer
Dielectric Etch
The goal of the contact or via etch is a minimum dimension, high aspect ratio hole in silicon dioxide with straight sidewalls, and selectivity to polysilicon, silicide, or metal. High density plasma source are required and the operating pressures are between 5 to 10 mTorr for the single wafer reactors. A variety of process gases utilizing fluorine, carbon, and oxygen are employed to achieve controlled polymer deposition during etch, resulting in the desired vertical sidewalls. Process byproducts, such as CO and SiF4 are added with the reactants to help control resist erosion and improve etch selectivity.
The tool illustrated here is a special kind of multi-chamber tool called a “cluster tool” that can perform multiple sequential operations automatically.
Plasma Dielectric Etches
CHF3 *
CF4
C2F6
C3F8
CO *
Diluents Ar He N2
CO2 O2
SF6
SiF4
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 19

20. Cleaning Critical Cleaning Photoresist Strips Pre-Deposition Cleans
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Critical Cleaning
Photoresist Strips
Pre-Deposition Cleans
Cleaning
In semiconductor processes, everything starts with a clean. The term “cleaning” is somewhat a misnomer. Experts in this field usually refer to this process as “wafer surface preparation” because wafers are not just cleaned but have their surfaces left in a precise chemical state that allows the next process step to be properly performed.
There are three major types of cleans used: Critical cleans, photoresist strips, and pre-deposition cleans.
Critical cleans are done for front-end processes and use strong acids (before metalization layers, which are sensitive to acid damage, are present). Photoresist strips are also done with strong acids during the front-end processes but must be done with solvents after the metalization process steps. Pre-deposition cleans are also done with solvents, however these processes are shifting to dry cleaning technologies.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 20

21. Critical Cleaning Process Conditions
Contact locations
Process Conditions
Temperature: Piranha Strip is 180 degrees C.
Critical Cleaning
Most wafer manufacturers use a cleaning method developed by RCA in The 3-step process starts with an SC1 solution (ammonia, hydrogen peroxide and ultrapure water) to remove organic impurities and particles from the wafer surface. Next, natural oxides and metal impurities are removed with hydrofluoric acid, and finally, the SC2 solution, (hydrochloric acid and hydrogen peroxide), causes super clean new natural oxides to grow up on the surface. This figure shows the RCA clean, which is the workhorse of the semiconductor industry. Because this process uses acids, it can only be used on FEOL processes. There is a trend to reduce acid concentration for these processes.
RCA Clean
SC1 Clean (H2O + NH4OH + H2O2) *
* SC2 Clean (H2O + HCl + H2O2) *
Piranha Strip
* H2SO4 + H2O2 *
Nitride Strip
H3PO4 *
Oxide Strip
HF + H2O *
Dry Strip
N2O O2
CF4 + O2 O3
Solvent Cleans
NMP
Proprietary Amines (liquid)
Dry Cleans HF
O2 Plasma
Alcohol + O3
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 21

22. Thin Films Chemical Vapor Deposition (CVD) Dielectric CVD Tungsten
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Chemical Vapor Deposition (CVD) Dielectric
CVD Tungsten
Physical Vapor Deposition (PVD)
Chamber Cleaning
Thin Films
Thin film processes are used to interconnect the transistors on a chip and make them into a functioning device. Chemical Vapor Deposition, or CVD is a broad class of processes using controlled chemical reactions to create layers on wafers. Prior to deposition, the wafer is usually cleaned with a Dry Plasma Etch process using either sulfur hexafluoride or a combination of tetrafluoromethane and oxygen.
Special hybrids of silicon and metal called silicides can be used to create conductive layers. For example, tungsten hexafluoride is used to create a tungsten silicide layer. A variant of CVD called Plasma-Enhanced Chemical Vapor Deposition, or PECVD, uses a gas plasma to lower the temperature required to obtain a chemical reaction and achieve film deposition. Cleaning of CVD chambers is usually done using nitrogen trifluoride plasma.
Metals like aluminum, tungsten, and copper are used to create conductive layers on a device. They are generally applied with by a process called sputtering or alternatively, “physical vapor deposition”, or PVD. Sputtering uses a cathode to create an argon plasma which bombards the source metal. The dislodged metal molecules are focused by a “lens” of radiation-absorbent material, called a collimator, and deposited in a thin film on the surface of the wafer.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 22

23. Chemical Vapor Deposition (CVD) Dielectric
LPCVD
Chamber
Transfer
Gas Inlet
Exhaust
RF Power
Wafer
Metering
Pump
Inert Mixing
Gas
Process Gas
Vaporizer
Direct
Liquid
Injection
TEOS
Source
Chemical Reactions
Si(OC2H5)4 + 9 O3  SiO2 + 5 CO + 3 CO H2O
Process Conditions (ILD)
Flow Rate: 100 to 300 sccm
Pressure: 50 Torr to Atmospheric
CVD Dielectric O2 O3
TEOS *
TMP *
Chemical Vapor Deposition (CVD)
Intermetal Dielectric
In order to fill the high aspect ratio gaps between adjacent metal lines, the intermetal dielectric process requires even more sophisticated techniques. The Plasma Enhanced (PE) CVD TEOS and Ozone TEOS processes can be alternated with intermediate etch backs (argon sputter or CF4 etch) to fill gaps with aspect ratios up to two. Theses are complex processes with multiple handoffs between deposition and etch reaction chambers. This procedure is best performed on a cluster tool, where wafers can be shuttled back and forth between the various modules automatically. Here, rapid response of the equipment control functions is critical to achieving good throughput. The pressure for these processed varies for the application, with PECVD running at below 10 Torr, Ozone TEOS processes from running at 50 Torr up to 1 atmosphere, and the etchback at 100 to 500 mTorr. For technologies requiring higher aspect ratio fills, equipment with high density plasma deposition operating at very low pressure of under 10 mTorr is required.
CVD Barriers
Another process using chemical vapor deposition forms a barrier between the wafer surface interconnection layers. Barrier layers prevent mobile ions from traveling to sensitive junctions and prevent reactive gases from etching exposed oxides. The most widely used barrier material for interconnects is titanium nitride, which can also be deposited through reactive sputter deposition.
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 23

24. Chemical Vapor Deposition (CVD) Tungsten
Input
Cassette
Output
Cassette
Chemical Reactions
WF6 + 3 H2  W + 6 HF
Process Conditions
Flow Rate: 100 to 300 sccm
Pressure: 100 mTorr
Temperature: 400 degrees C.
Wafer
Hander
Wafers
Multistation Sequential
Deposition Chamber
CVD Dielectric
WF6 * Ar H2 N2
Chemical Vapor Deposition (CVD) Tungsten
Tungsten blanket deposition is widely employed for filling contact holes and vias. In this 400°C process, WF6 is reacted with silane for the initial seed layer deposition. In the subsequent stage, the reactants are tungsten hexafluoride and hydrogen, which is a faster process for depositing the bulk film. Both processes can be run at pressures under 100 mTorr in either a single wafer or a multi-stage reactor. By running the silane-based process first, this reaction sequence protects against free radical fluorine from the WF6 + H2 reaction etching exposed metal, oxides or silicon. During the deposition the tungsten overflows the contact or via hole and then must be etched back uniformly so that the titanium nitride, or glue layer, is not damaged. Plasma cleans are performed on a routine basis using C2F6 in order to minimize particles.
The tungsten plug process is eliminated when copper is used because the conductivity of copper allows dramatic improvements in device performance.
Water-cooled
Showerheads
Resistively
Heated Pedestal
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 24

25. Physical Vapor Deposition (PVD)
Chambers
Cluster Tool
Configuration
Wafers
Transfer
Chamber
Loadlock
Process Conditions
Pressure: < 5 mTorr
Temperature: 200 degrees C.
RF Power:
Reactive
Gases
PVD Chamber N S
Cryo Pump
Barrier Metals
SiH4 Ar N2
Ti PVD Targets *
Physical Vapor Deposition (PVD)
PVD Metals
Both non-reactive argon sputtering and reactive nitrogen sputtering are employed in depositing a variety of metals, including titanium, titanium nitride, and aluminum copper alloys. These processes are performed at low operating pressure (less than 5 mTorr) to maximize film density and deposition rate: More scattering at higher pressures slows the deposition rate and leads to glancing angles for deposition, leading to a less dense film. Because of the reactivity of some of these materials, multi-chamber tools called “cluster tools” have been developed which allow multiple sequential operations automatically without exposing the wafer to air. These cluster configurations also provide leverage in manufacturing efficiency.
CVD Metals
Advanced wiring technology uses copper for both via fill and interconnects. This application puts unique demands on the deposition tools, especially involving delivery of precursors to the reactor, and the requirements for clustered equipment involving multiple process steps without breaking vacuum.
Transfer
Chamber
e - +
Wafer
Argon &
Nitrogen
Backside
He Cooling
DC Power
Supply (+)
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 25

26. Chamber Wall Cross-Section
Chamber Cleaning
Water-cooled
Showerheads
Multistation Sequential
Deposition Chamber
Resistively
Heated Pedestal
Chemical Reactions
Oxide Etch: SiO2 + C2F6  SiF4 + CO2 + CF4 + 2 CO
Process Conditions
Flow Rates: 10 to 300 sccm
Pressure: 10 to 100 mTorr
RF Power: 100 to 200 Watts
Aluminum
Surface Coating
Process Material Residue
Chamber Cleaning
C2F6 *
NF3
ClF3
Chamber Cleaning
Insitu chamber cleaning processes are used to extend the time that machines can be operated between manual chamber cleaning processes.
Vacuum chambers are typically fabricated from 6061 aluminum alloy and have either an anodized coating (aluminum oxides) or an aluminum fluoride (AlF) passivation coating. Chamber hard-cleans, are performed infrequently (depending on process, a interval of typically one week to monthly). Current generation semiconductor vacuum process tool designs have evolved to a level of sophistication where the surface composition and texture of the process components is factored into the process design and in many cases is actively used to capture effluent and by-products.
In deposition or etching processes, reaction by-products coat the walls of the vacuum chambers. After these by-product coatings become too thick, they flake off in small particles and deposit on the wafer, causing “killer” defects on the electronic circuits being manufactured. The surface of the vacuum chamber is treated to provide the ability to resist corrosion by aggressive cleaning agents or process chemicals, hardness to resist physical wear, and surface texture to minimize flaking (rough surfaces perform better than smooth surfaces in this regard).
Gas-phase cleaning has many advantages. Gas cleaning is free from manual labor and is total cleaning, not only of the chamber, but cleans from the supply pipe up to the exhaust pipe. It offers safe and complete cleaning and results in shorter MTOL (Mean Time Off Line).
Chamber Wall Cross-Section
* High proportion of the total product use
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 26

27. Planarization Oxide Planarization Metal Planarization Planarization
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Oxide Planarization
Metal Planarization
Planarization
Wafers are polished in a series of chemical and mechanical polishing processes called CMP.
This process enables multiple layers of semiconductor metalization to be deposited, allowing denser interconnection layers.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 27

28. Chemical Mechanical Planarization (CMP)
Platen
Polishing
Head
Pad
Conditioner
Carousel
Sweep Slide
Load/Unload
Station
Wafer Handling
Robot & I/O
Process Conditions (Oxide)
Flow: 250 to 1000 ml/min
Particle Size: 100 to 250 nm
Concentration: 10 to 15%, 10.5 to 11.3 pH
Process Conditions (Metal)
Flow: 50 to 100 ml/min
Particle Size: 180 to 280 nm
Concentration: 3 to 7%, pH
Wafer
Carrier
Polishing Pad
Chemical Mechanical Planarization (CMP)
Oxide Planarization
Chemical Mechanical Polish (CMP) provides planarity for the oxide dielectric used at the metallization level. Advanced development is in the area of copper and aluminum planarization. The chemistry of the slurry, the nature of the pad, and the mechanics of the tool are all critical to achieving global planarization over a 300 mm wafer.
Metal Planarization
Chemical Mechanical Polish (CMP) provides planarity for the tungsten plug used at the metallization level. Dishing is an issue for future processes, especially on soft metals such as aluminum and copper.
Slurry
Delivery
Backing (Carrier) Film
Polyurethane
Pad
Pad Conditioner
Abrasive
CMP (Oxide)
Silica Slurry
KOH *
NH4OH
H2O
CMP (Metal)
Alumina *
FeNO3 *
Wafer
Platen
* High proportion of the total product use.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 28

29. Test and Assembly Electrical Test Probe Die Cut and Assembly
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
Etch
Ion
Implantation
Planarization
Test &
Assembly
Design
Wafer
Preparation
Electrical Test Probe
Die Cut and Assembly
Die Attach and Wire Bonding
Final Test
Test & Assembly
Test and assembly operation are performed out of the cleanroom wafer fab. In these operations, chips are tested, put into packages, then retested.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 29

30. Electrical Test Probe Defective IC
n-well
p-channel transistor
p-well
n-channel transistor
p+ substrate
bonding pad
nitride
Metal 2
Electrical Test Probe
After the final passivation layers are applied, the entire wafer goes through backside preparation or backlap, which thins the wafer to allow better heat dissipation and removes stress fractures which could cause breakage.
Each finished wafer may contain several hundred individual devices called “die.” Semiconductor device manufacturers use automated methods to test each device on the wafer before it is broken into “chips.”
A probe tester uses needle-like “probes” to contact the bonding pads (the circuit connection points) on each device and check its operation. Devices that fail the test are marked with colored dye spot so they won't be carried further into the production process.
The efficiency of a given fab is determined by it's yield: the ratio of functional die to total die. State-of-the-art fabs typically operate at more than 90% yield within 18 months of startup.
Defective IC
Individual integrated circuits are tested to distinguish good die from bad ones.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 30

31. Die Cut and Assembly Good chips are attached to a lead frame package.
After electrical test, the wafer is scored with a special diamond saw and broken into individual die. The marked (non-functional) die are discarded and functional die are passed on into the wire bonding process.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 31

32. Die Attach and Wire Bonding
lead frame
gold wire
bonding pad
Die Attach and Wire Bonding
Once separated into individual die, the functional devices are attached to a lead frame assembly. A drop of precisely engineered compound is placed beneath the die to glue it to the lead frame assembly and provide good electrical grounding and heat transfer for the silicon device.
Aluminum or gold leads are attached via thermal compression or ultrasonic welding. The automated process attaches the ultra-thin wires (about 30 µm in diameter, 1/3 the diameter of a human hair) between each device bonding pad and a connector of the lead frame.
There are thousands of different packages available, each specially engineered to provide a specific benefit such as small package size, high frequency information transmission or protection from extreme environmental conditions such as heat, cold or moisture.
connecting pin
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 32

33. Final Test
Chips are electrically tested under varying environmental conditions.
Final Test
After wire bonding is completed, the packaging is completed by molding the device into a plastic enclosure.
Packages are precisely engineered to provide good thermal conductivity, easy assembly into printed circuit boards and protection from damaging environmental conditions.
These packages are often tested again and sorted by performance speed because faster chips sell for higher margins than slower chips. Some chips receive special testing by being place in high temperature ovens or in warm, humid environments or are subject to repeated cycling between extreme hot and cold temperatures. These tests help engineers ensure that the product reliability is within specified limits.
After final testing, the chips are packed into shipping containers and shipped to customers.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 33

34. References
1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT, Austin Community College, January 2, 1997.
2. Semiconductor Processing with MKS Instruments, Inc.
3. Worthington, Eric. “New CMP architecture addresses key process issues,” Solid State Technology, January 1996.
4. Leskonic, Sharon. “Overview of CMP Processing,” SEMATECH Presentation, 1996.
5. Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997.
6. CVD Tungsten, Novellus Sales Brochure, 7/96.
7. Fullman Company website. “Fullman Company - The Semiconductor Manufacturing Process,”
8. Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit,” Scientific American Special Issue: The Solid State Century, January 22, 1998.
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34