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Processes of Fabrication 1. 2 N Transistor Structure Review.

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Presentation on theme: "Processes of Fabrication 1. 2 N Transistor Structure Review."— Presentation transcript:

1 Processes of Fabrication 1

2 2 N Transistor Structure Review

3 3 P Transistor Structure Review

4 4 Semiconductor Review Create by doping a pure silicon crystal Diffuse impurity into crystal lattice Changes the concentration of carriers Electrons Holes More doping -> more carriers available n-type semiconductor (n or n+) Majority carrier: electrons Typical impurity: Arsenic (Column V) p-type semiconductor (p or p+) Majority carrier: holes Typical impurity: Boron (Column III) nn+ pp+

5 5 Other key working materials Insulator - Silicon Dioxide (SiO 2 ) Used to insulate transistor gates (thin oxide) Used to insulate layers of wires (field oxide) Can be grown on Silicon or Chemically Deposited Polysilicon - polycrystalline silicon Key material for transistor gates Also used for short wires Added by chemical deposition Metal - Aluminum (…and more recently Copper) Used for wires Multiple layers common Added by vapor deposition or sputtering

6 6 CMOS Processing Wafer Processing Photolithography Oxide Growth & Removal Material Deposition & Removal Diffusion of Impurities Putting it all together

7 7 A View of the Cleanroom AMDs Dresden Fab - Source: AMD Corporation

8 8 Creating Wafers - Czochralski Method Start with crucible of molten silicon (1425 o C) Insert crystal seed in melt Slowly rotate / raise seed to form single crystal boule After cooling, slice boule into wafers & polish Crucible Molten Silicon

9 9 Definitions Wafer – a thin circular silicon Each wafer holds hundreds of dies Transistors and wiring are made from many layers (usually 10 – 15) built on top of one another the first half-dozen or so layers define transistors the second define the metal wires between transistors Lambda ( ) – the smallest resolvable feature size imprinted on the IC; it is roughly half the length of the smallest transistor 0.2 m IC – the smallest transistors are approximately 0.2 m in length ( = 0.1 m)

10 10 Wafer Structure Current production: 200mm (10) Newest technology: 300mm (12)

11 11 Processing Wafers All dice on wafer processed simultaneously Each mask has one image for each die The basic approach: Add & selectively remove materials Metal - wires Polysilicon - gates Oxide Selectively diffuse impurities Photolithography is the key

12 12 Fabrication processes IC built on silicon substrate: some structures diffused into substrate; other structures built on top of substrate. Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (SiO 2 ) is insulator.

13 13 Photolithography Coat wafer with photoresist (PR) Shine UV light through mask to selectively expose PR Use acid to dissolve exposed PR Now use exposed areas for Selective doping Selective removal of material under exposed PR Wafer Photoresist Mask UV Light

14 14 Adding Materials Add materials on top of silicon Polysilicon Metal Oxide (SiO 2 ) - Insulator Methods Chemical deposition Sputtering (Metal ions) Oxidation

15 15 Oxide (Si0 2 ) - The Key Insulator Thin Oxide Add using chemical deposition Used to form gate insulator & block active areas Field Oxide (FOX) - formed by oxidation Wet (H 2 0 at 900 o C o C) or Dry (O 2 at 1200 o C) Used to insulate non-active areas Silicon Wafer SiN / SiO 2 FOX SiO 2 Thin Oxide

16 16 Patterning Materials using Photolithography Add material to wafer Coat with photoresist Selectively remove photoresist Remove exposed material Remove remaining PR

17 17 Diffusion Introduce dopant via epitaxy or ion implant e.g. Arsenic (N), Boron (P) Allow dopants to diffuse at high temperature Block diffusion in selective areas using oxide or PR Diffusion spreads both vertically, horizontally

18 18 CMOS Well Structures Need to accommodate both N, P transistors Must implement in separate regions - wellls (tubs) N-well P-well Alternate approach: Silicon on Insulator (SOI) n-well p substrate n well n substrate p well p-well

19 19 Detailed View - N-Well Process Overall chip doped as p substrate, tied to GND Selected well areas doped n, tied to VDD GndVDD

20 20 P substrate CMOS Processing - Creating an Inverter Substrate Well Active Areas Gates Diffusion Insulator Contacts Metal wafer n well

21 21 P substrate CMOS Mask Layers Determine placement of layout objects Color coding specifies layers Layout objects: Rectangles Polygons Arbitrary shapes Grid types Absolute (micron) Scaleable (lambda) wafer n well

22 22 Mask Generation Mask Design using Layout Editor user specifies layout objects on different layers output: layout file Pattern Generator Reads layout file Generates enlarged master image of each mask layer Image printed on glass reticle Step & repeat camera Reduces & copies reticle image onto mask One copy for each die on wafer Note importance of mask alignment

23 23 Simple cross section substrate n+ p+ substrate metal1 poly SiO 2 metal2 metal3 transistor via

24 24 Transistor structure n-type transistor:

25 micron transistor (Bell Labs) poly silicide source/drain gate oxide

26 Fabrication and Layout Slide 26 Ion Implantation 180 kV Resolving Aperture Ion Source Equipment Ground Acceleration Tube 90° Analyzing Magnet Terminal Ground 20 kV Focus Neutral beam and beam path gated Beam trap and gate plate Wafer in wafer process chamber X - axis scanner Y - axis scanner Neutral beam trap and beam gate Gases Ar AsH 3 B 11 F 3 * He N 2 PH 3 SiH 4 SiF 4 GeH 4 Solids Ga In Sb Liquids Al(CH 3 ) 3 Process Conditions Flow Rate: 5 sccm Pressure: Torr Accelerating Voltage: 5 to 200 keV

27 Fabrication and Layout Slide 27 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

28 Fabrication and Layout Slide 28 Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor

29 Fabrication and Layout Slide 29 Polysilicon Patterning Use same lithography process to pattern polysilicon

30 Fabrication and Layout Slide 30 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n- well contact

31 Fabrication and Layout Slide 31 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self- aligned gates because it doesnt melt during later processing

32 Fabrication and Layout Slide 32 N-diffusion Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

33 Fabrication and Layout Slide 33 N-diffusion Strip off oxide to complete patterning step

34 Fabrication and Layout Slide 34 P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

35 Fabrication and Layout Slide 35 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

36 Fabrication and Layout Slide 36 Metallization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

37 Fabrication and Layout Slide 37 Physical Vapor Deposition (PVD) Barrier Metals SiH 4 Ar N 2 Ti PVD Targets * Physical Vapor Deposition Chambers Cluster Tool Configuration Transfer Chamber Loadlock Wafers PVD Chamber Transfer Chamber Cryo Pump Wafer NSN + e - Backside He Cooling Argon & Nitrogen Reactive Gases DC Power Supply (+) Process Conditions Pressure: < 5 mTorr Temperature: 200 degrees C. RF Power:

38 Fabrication and Layout Slide 38 Schematic Diagram of Vacuum Evaporation System (PVD)

39 Fabrication and Layout Slide 39 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f/2 E.g. = 0.3 m in 0.6 m process

40 Fabrication and Layout Slide 40 Simplified Design Rules Conservative rules to get you started

41 Fabrication and Layout Slide 41 Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4 / 2 sometimes called 1 unit For 0.6 m process, W=1.2 m, L=0.6 m

42 Fabrication and Layout Slide 42 Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip!

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