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BEOL Al & Cu. Overview Review BEOL Why is it important? Copper vs Al Technology Process technology to achieve the final product Some Integration issues.

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Presentation on theme: "BEOL Al & Cu. Overview Review BEOL Why is it important? Copper vs Al Technology Process technology to achieve the final product Some Integration issues."— Presentation transcript:

1 BEOL Al & Cu

2 Overview Review BEOL Why is it important? Copper vs Al Technology Process technology to achieve the final product Some Integration issues and work-arounds

3 Chip manufacturing: Snap shot Physical “Layout” Design Creating the chip Testing Electrical Chip Design RC Blue Print- Photo “negative” “Print” Quality Control

4 Creating the chips Creating the devices (transistors, capacitors, resistors) Connecting the devices (wiring) Packaging Front End of the Line FEOL Back End of the Line BEOL Device 1 Device 2 Device 3Device 4 Metal Contact

5 Chip - Simplified Schematic What if you want to connect Device 3 to another device 5 just at the back of Device 3? Device 1 Device 2 Device 3Device 4 Metal Contact

6 Chip - Simplified Schematic Device 1 Level 1 Level 2 Device 2 Device 3Device 4 Many layers of metal are necessary for current Chips (typically 4 to 5) Up to 8 metal layers are manufacturable in the top class manufacturing units (called fabs) Via

7 Intel 7 metal SEM (90 nm node) © Intel

8 BEOL: Importance For older generation, BEOL was an important factor in the yield of the chip. The speed of the chip was determined by the transistors (FEOL) What is yield? Importance has been increasing recently and will continue to do so For newer generation, BEOL may be important in both yield and speed More layers than FEOL => more likely to fail. Hence the yield impact Transistors may switch fast, but the signal has to go through wires!

9 Estimates on delay ©

10 BEOL Processes Photo Lithography Deposition (Chemical Vapor Deposition, Physical Vapor deposition, Electrochemical Deposition) Removal (Chemical Mechanical Polishing, Etching) Anneal

11 Overview Review BEOL Why is it important? Copper vs Al Technology Aluminum Product : Details Aluminum/ W Process Flow (partial) Litho, Dep, Removal Aluminum process flow (complete) Cu Process Flow Process technology to achieve the final product Some Integration issues and work-arounds

12 Relevant Conductor Properties Some of the important & relevant properties Resistivity (micro ohm-cm) Litho Process compatibility eg. Will it react with photo resist? Melting point Thermal Expansion coefficient Diffusivity in silicon di oxide (or any other insulator) Adhesion to the insulator Inter-atomic distances (stress) Process Crystal orientations, grain sizes Step coverage

13 BEOL Materials: Al vs Cu Conductor: Copper OR Aluminum Aluminum : Older generation (mostly up to 0.18 um) Copper: 0.18 um and below Insulator: Oxide (silicon-di-oxide) or Low-K materials What is Low-k? Low di-electric constant Why? Capacitance Via Metal Via Metal

14 BEOL Materials: Al vs Cu Low-K: Being introduced now Will not be discussed in detail in the class Few pointers, in the Process Integration chapter Aluminum and Copper products Aluminum technologyCopper technology Al WW Cu Al metal lines are connected by Tungsten Via Copper lines are connected by copper via

15 Aluminum Process: General Aluminum technology Aluminum Resistivity: 2.6  ohm-cm Copper Resistivity: 1.7  ohm-cm W Resistivity: 5.7  ohm-cm W Via: Why? Easier to Process W is higher resistivity, but via is short ==> Lower impact on the overall resistance Al WW

16 Aluminum Process: General Aluminum technology Other relevant information: Both W and Al need “Liners” Ti/TiN liners Diffusion Barriers Adhesion enhancement Stress Reduction (==> better reliability) Al WW

17 Aluminum Process: Detail (a bit) Aluminum technology

18 Aluminum Process: General Oxide deposition - CVD Shape Definition - Litho Oxide Removal -Dry etch with plasma Ti/TiN Deposition - PVD /CVD W Deposition -CVD W Removal - CMP Ti/TiN Deposition- PVD /CVD Al Deposition PVD Ti/TiN Deposition - PVD/CVD Shape Definition - Litho Ti/TiN/Al Removal - Dry etch with plasma Oxide deposition - CVD

19 Digression: Intel 7 metal SEM (90 nm node) Pitch = space+width Normally pitch means minimum pitch in a layer Usually M1 pitch is tighter than poly Note M7 is very large (power lines) © Intel

20 Digression: Metal line widths M1 is usually very small (eg 200 nm) M1 pitch is typically tighter than poly pitch M2, M3, etc are slightly larger (eg 250 nm) Last metal (and the last but one) can be very large (eg 400 nm) Why? After lot of layers are built, the photo margin tends to be low for small line width/spaces Last metal tend to carry lot of current and you need the width, to reduce resistance Fewer wires are needed. Space is available. So why not?

21 Oxide Deposition Aluminum Process: Details (more) Densification CMP Post CMP Clean Photo resist coatLitho-exposeLitho-Develop Etch Resist Strip Liner Dep (PVD/CVD) Other steps: Later on Tunsten Dep Tunsten CMP Liner Dep Al Dep

22 Copper Process-General Damascene Process Single Damascene vs Dual Damascene Lower resistivity Reduced power consumption, reduced heating, longer battery life... More reliable connection (long term) Lower processing cost with Dual Damascene At least, that is the theory! Faster diffusion Difficult to etch/ Process not as mature as Al process

23 Damascene Method Initiated by IBM (practiced in ancient times for pottery designs)

24 Damascene Method Example of Single Damascence Process DepEtch DepPolish Single, because one layer is created in one damascene step Polishing of Copper makes this possible

25 Damascene Method Example of Dual Damascence Process Dual, because two layer are created in one damascene step Etch DepPolish

26 CMP Tool: Schematic Controlled Pressure Rotation Rate Controlled Rotation Rate Controlled slurry flow rate and temp Cu Disk Pad Removal is mechanical (abrasive particles) and chemical (dissolution) Inhibitors added for controlled removal

27 CMP removal mechanism Copper Pad Removal in these regions No Removal in this region ==> non planar surface --> planar surface

28 CMP: Basics Pressure, Velocity - Removal Rate Chemical Dissolution Controlled Removal ==> Dissolution Inhibitors Smooth Surface ==> Surfactants

29 BEOL Process-General Cu or Al process: Liners are present Cu - Ta/TaN liners Also has PVD ‘seed’ layer of copper Al - Ti/TiN liners Contacts from Transistors to the M1 Always W CMP in Cu newer challenges Main deposition is Electrochemical Grain Size (resistivity, electro migration) void free fill

30 BEOL Summary Focus chiefly on conductor (insulator options & processes not discussed in detail) Al vs Cu processes Al -etch / Cu Damascene (CMP) Al -via is W / Cu- via is Cu Al & Cu: Contact is W Not all the details of Al vs Cu discussed now Overall, the processes involved are Litho, PVD, CVD, Electrochem Dep, Etch, Anneal Comparison: Production of a chemical: Flow sheet, unit operations


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