2Overview Review BEOL Why is it important? Copper vs Al Technology Process technology to achieve the final productSome Integration issues and work-arounds
3Chip manufacturing: Snap shot Electrical Chip DesignRCPhysical “Layout” DesignBlue Print-Photo“negative”Creating the chipReviewTesting“Print”Quality Control
4Creating the chips Review Front End of the Line FEOL Back End of the LineBEOLCreating the devices (transistors, capacitors, resistors)Connecting the devices (wiring)ReviewMetalContactSilicon WaferDevice 1Device 2Device 3Device 4Packaging
5Chip - Simplified Schematic Silicon WaferDevice 1Device 2Device 3Device 4MetalContactReviewWhat if you want to connect Device 3 to another device 5 just at the back of Device 3?
6Chip - Simplified Schematic Level 1Level 2ViaDevice 1Device 2Device 3Device 4Silicon WaferReviewMany layers of metal are necessary for current Chips (typically 4 to 5)Up to 8 metal layers are manufacturable in the top class manufacturing units (called fabs)
8BEOL: ImportanceImportance has been increasing recently and will continue to do soFor older generation, BEOL was an important factor in the yield of the chip. The speed of the chip was determined by the transistors (FEOL)What is yield?More layers than FEOL => more likely to fail. Hence the yield impactFor newer generation, BEOL may be important in both yield and speedTransistors may switch fast, but the signal has to go through wires!
11Overview Review BEOL Why is it important? Copper vs Al Technology Aluminum Product : DetailsAluminum/ W Process Flow (partial)Litho, Dep, RemovalAluminum process flow (complete)Cu Process FlowProcess technology to achieve the final productSome Integration issues and work-arounds
12Relevant Conductor Properties Some of the important & relevant propertiesResistivity (micro ohm-cm)Litho Process compatibilityeg. Will it react with photo resist?Melting pointThermal Expansion coefficientDiffusivity in silicon di oxide (or any other insulator)Adhesion to the insulatorInter-atomic distances (stress)ProcessCrystal orientations, grain sizesStep coverage
13BEOL Materials: Al vs Cu Conductor: Copper OR AluminumAluminum : Older generation (mostly up to 0.18 um)Copper: 0.18 um and belowInsulator:Oxide (silicon-di-oxide) or Low-K materialsWhat is Low-k?Low di-electric constantWhy?CapacitanceMetalMetalViaViaVia
14BEOL Materials: Al vs Cu Low-K:Being introduced nowWill not be discussed in detail in the classFew pointers, in the Process Integration chapterAluminum and Copper productsAl metal lines are connected by Tungsten ViaCopper lines are connected by copper viaAluminum technologyCopper technologyAlWCu
15Aluminum Process: General Aluminum technologyAlWAluminum Resistivity: 2.6 m ohm-cmCopper Resistivity: 1.7 m ohm-cmW Resistivity: 5.7 m ohm-cmW Via: Why?Easier to ProcessW is higher resistivity, but via is short==> Lower impact on the overall resistance
16Aluminum Process: General Aluminum technologyAlWOther relevant information:Both W and Al need “Liners”Ti/TiN linersDiffusion BarriersAdhesion enhancementStress Reduction (==> better reliability)
17Aluminum Process: Detail (a bit) Aluminum technologyAluminum technology
20Digression: Metal line widths M1 is usually very small (eg 200 nm)M1 pitch is typically tighter than poly pitchM2, M3, etc are slightly larger (eg 250 nm)Last metal (and the last but one) can be very large (eg 400 nm)Why?After lot of layers are built, the photo margin tends to be low for small line width/spacesLast metal tend to carry lot of current and you need the width, to reduce resistanceFewer wires are needed. Space is available. So why not?
21Aluminum Process: Details (more) CMPOxide DepositionTunsten CMPTunsten DepAl DepResist StripPhoto resist coatLitho-DevelopLitho-exposeLiner Dep (PVD/CVD)Liner DepEtchPost CMP CleanDensificationOther steps: Later on
22Copper Process-General Lower resistivityReduced power consumption, reduced heating, longer battery life...More reliable connection (long term)Lower processing cost with Dual DamasceneAt least, that is the theory!Faster diffusionDifficult to etch/ Process not as mature as Al processDamascene ProcessSingle Damascene vs Dual Damascene
23Damascene MethodInitiated by IBM (practiced in ancient times for pottery designs)
24Damascene Method Example of Single Damascence Process Single, because one layer is created in one damascene stepPolishing of Copper makes this possiblePolishDepEtchDep
25Damascene Method Example of Dual Damascence Process Dual, because two layer are created in one damascene stepPolishDepEtchEtch
26CMP Tool: SchematicControlled PressureRotation RateControlled slurryflow rate and tempCu DiskPadControlled Rotation RateRemoval is mechanical (abrasive particles) and chemical (dissolution)Inhibitors added for controlled removal
27CMP removal mechanism Copper No Removal in this region Removal in these regionsPad==> non planar surface --> planar surface
29BEOL Process-General Cu or Al process: Liners are present Cu - Ta/TaN linersAlso has PVD ‘seed’ layer of copperAl - Ti/TiN linersContacts from Transistors to the M1Always WCMP in Cunewer challengesMain deposition is ElectrochemicalGrain Size (resistivity, electro migration)void free fill
30BEOL SummaryFocus chiefly on conductor (insulator options & processes not discussed in detail)Al vs Cu processesAl -etch / Cu Damascene (CMP)Al -via is W / Cu- via is CuAl & Cu: Contact is WNot all the details of Al vs Cu discussed nowOverall, the processes involved areLitho, PVD, CVD, Electrochem Dep, Etch, AnnealComparison: Production of a chemical: Flow sheet, unit operations