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1 Pertemuan 5 Fabrikasi IC CMOS Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01.

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Presentation on theme: "1 Pertemuan 5 Fabrikasi IC CMOS Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01."— Presentation transcript:

1 1 Pertemuan 5 Fabrikasi IC CMOS Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01

2 2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menyebutkan proses fabrikasiIC CMOS.

3 3 IC Fabrication Sumber: http://mems.cawru.edu/shortcourse/figure/I_2.1.gif

4 4 Silicon Processing 2 Silicon wafer Sumber: http://www.amd.com Diameter Wafer Die sites

5 5 Material Growth & Deposition Silicon oxide Silicon wafer O 2 flow Silicon wafer SiO 2 layer X Si X ox Growth phase Final structure Substrate CVD oxide SiO 2 molecues

6 6 IC Layers Ion implanter Ion source accelerator Magnetic mass separator Ion beam wafer Ion Silicon wafer Silicon nuclei electron cloud x 0

7 7 Lythography poly substrate poly substrate After oxide deposition After CMP GlassPattern on underside

8 8 Lythography Spinning wafer Photoresist spray Vcuum chuck Resist application Photoresist coating Coated wafer Wafer Flat resist Edge bead Beading

9 9 Lythography UV Reticle Resist-coated Wafer surface Reticle shadow Projection optics (not shown) Exposure step

10 10 Lythography Wafer UV Reticle Resist Exposure pattern Wafer After development and rinsing Hardened resist layer

11 11 Lythography Hardened resist layer Substrate Initial patterning of resist Oxide layer After etching process Substrate Pattern oxide layer

12 12 Lythography Incoming ion beam Substrate Arsenic ions Doped n-type region Substrate n+

13 13 CMOS Process Flow p-epitaxial layer p+ substrate a. Starting wafer with epitaxial layer n-well p, Na b. Creation of n-well in p-epitaxial layer n-well p, Na c. Active area definition using nitride / oxide p, Na n-well d. Silicon etch Nitride p, Na n-well e. Field oxide growth FOX p, Na n-well f. Surface preparation

14 14 CMOS Process Flow a. Gate oxide growth p, Na n-well b.Gate oxide growthPoly gate deposition & patterning p, Na n-well poly c. pSelect mask and implant p, Na n-well resist Boron implant p+ implant d. nSelect mask and implant p, Na n-well resist Arsenic implant n+ implant

15 15 CMOS Process Flow a. After anneal and CVD oxide p, Na n-well b. After CVD oxide active contact, W plugs p, Na n-well W W WW W W c. Metal 1 coating and patterning p, Na n-well Metal 1 Metal bonding pad Bond Bonding pad Ke pin IC Overglass wire

16 16 Design Rules wpwp wpwp S p-p poly W p = minimum width of polysilicon line S p-p = minimum poly-topoly spacing

17 17 RESUME IC Fabrication: Flow of process. Silicon Processing: wafer, material growth, deposition. Lythography: pattern, photoresist coating, exposure steps, etching, n-type. CMOS Process flow. Design rules


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