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Pertemuan 5 Fabrikasi IC CMOS

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Presentation on theme: "Pertemuan 5 Fabrikasi IC CMOS"— Presentation transcript:

1 Pertemuan 5 Fabrikasi IC CMOS
Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01 Pertemuan 5 Fabrikasi IC CMOS

2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menyebutkan proses fabrikasiIC CMOS.

3 IC Fabrication Sumber:

4 Silicon Processing Silicon wafer 2 Diameter Wafer Die sites
Sumber: Diameter Wafer Die sites 2

5 Material Growth & Deposition
Silicon oxide Silicon wafer O2 flow SiO2 layer XSi Xox Growth phase Final structure Substrate CVD oxide SiO2 molecues

6 IC Layers Ion implanter Ion source accelerator Magnetic mass separator
Ion beam wafer Ion Silicon wafer Silicon nuclei electron cloud x

7 Lythography substrate After oxide deposition After CMP Glass
poly substrate After oxide deposition After CMP Glass Pattern on underside

8 Lythography Photoresist spray Spinning wafer Photoresist coating
Vcuum chuck Resist application Photoresist coating Coated wafer Wafer Flat resist Edge bead Beading

9 Lythography UV Exposure step Reticle Projection optics (not shown)
Resist-coated Wafer surface shadow Projection optics (not shown) Exposure step

10 Lythography UV Reticle Resist Wafer Exposure pattern Hardened
After development and rinsing Hardened resist layer

11 Lythography Hardened resist layer Oxide layer Substrate
Initial patterning of resist Oxide layer After etching process Pattern oxide layer

12 Lythography Arsenic ions Substrate Incoming ion beam
Doped n-type region n+

13 CMOS Process Flow p+ substrate a. Starting wafer with epitaxial layer
p-epitaxial layer p+ substrate a. Starting wafer with epitaxial layer n-well p, Na b. Creation of n-well in p-epitaxial layer c. Active area definition using nitride / oxide d. Silicon etch Nitride e. Field oxide growth FOX f. Surface preparation

14 CMOS Process Flow poly Arsenic implant Boron implant
a. Gate oxide growth p, Na n-well Gate oxide growthPoly gate deposition & patterning poly c. pSelect mask and implant resist Boron implant p+ implant d. nSelect mask and implant Arsenic implant n+ implant

15 CMOS Process Flow Bonding pad a. After anneal and CVD oxide
p, Na n-well b. After CVD oxide active contact, W plugs W c. Metal 1 coating and patterning Metal 1 Metal bonding pad Bond Bonding pad Ke pin IC Overglass wire

16 Design Rules wp poly Sp-p Wp = minimum width of polysilicon line
Sp-p = minimum poly-topoly spacing

17 RESUME IC Fabrication: Flow of process. Silicon Processing: wafer, material growth, deposition. Lythography: pattern, photoresist coating, exposure steps, etching, n-type. CMOS Process flow. Design rules

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