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Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course Technology

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Presentation on theme: "Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course Technology"— Presentation transcript:

1 Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course Technology

2 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET The process: manufacturing technology ► Overview of the steps and some machines

3 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Basic processing principles ► Layer growth or deposition: new material layer is formed over the entire surface of the wafer ► Patterning: some patterns are formed in the deposited layer  deposition of a photo-sensitive lack (photoresist)  photographing the pattern onto the lack  developing the photoresist: pattern formed in the resist layer  transferring the pattern from the resist to the material layer underneath by some kind of etching  removal of the resist ► In-depth deposition of external material: ion implantation (formerly: diffusion)

4 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET E.g. patterning ► The original pattern is on a so called photo-mask  made of chromium on glass substrate  many times larger than a chip ► Need for high level of accuracy:  0.03µm over 30cm!  ► Visible light:  = µm  deep UV needed!

5 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Monolithic IC-s Mono lit = single stone In-depth structure Surface structure (pattern) MFS – the major property of a process 15  m  0.18  m or less…

6 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET ► Layer growth / deposition:  growth of epitaxial layer (continue the Si-lattice but doped) today e.g.: IBE – ion-beam epitaxy: atomic layers are grown  oxidation (deposit/grow SiO 2 )  evaporation (e.g. deposit metal such as Al)  Other deposition methods, e.g.: sputtering CVD: chemical vapor deposition In-depth structure

7 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET ► The classical epitaxial growth  either from gas or from liquid phase  The crystalline structure of the Si wafer is perfectly continued by the layer grown Growth of epitaxial layers Si wafers ~1200 o C

8 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET ► Depending on the SiCl 4 /H 2 ratio  growth of a single crystalline layer  growth of poly-crystalline silicon – called poly-Si  etching off Si Growth of epitaxial layers Growth of oxide layers ► Thermal oxidation ( o C) ► Chemical Vapor Deposition (CVD)

9 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Vapor deposition ► Free mean path > size of the chamber ► Metallization: ~ µm Vacuum pump Si wafers Vacuum Evaporation source

10 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Sputtering ► Gas dis-charge is used to carry the material to be deposited from a cathode (e.g. Ar atmosphere) ► Using high frequency dielectrics can also be sputtered Si wafers To be deposited on the Si

11 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET ► Deposition of dopants (foreign atoms) in the silicon crystall to modify its properties In-depth structure Diamond lattice in 3D Simplified view in 2D Dopant from column V: extra electron DONOR n-type Si Dopant from column III: 1 less electron ACCEPTOR p-type Si

12 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET How to select where to dope? ► SiO 2 is an excellent mask against the flux of dopants Diffusion deep profile Ion implantation shallow profile Masked by a SiO 2 pattern

13 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET ► Deposition of dopants by diffusion  Dopants diffuse in the high temperature Si-lattice  The energy of the Si atoms helps the dopants move  Movement mechanisms: interstitial movement: movement by changing place with a Si atom movement along crystalline defects  In-depth distribution of dopants is determined by Fick's laws: In-depth structure

14 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Diffusion ► The solution is: ► Two steps  initial deposition / pre-fiffusion (e.g o C, 3 hours)  drive-in(e.g o C, 1 hours)

15 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Diffusion ► The diffusion furnace Masked by a SiO 2 pattern

16 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Ion implantation ► From an ion beam one selects the ions that target the Si and penetrate the lattice ► Initial distribution of deposited dopants depends on the energy and the dose of the ion beam ► Thermal treatment follows the implantation  restore the Si-lattice  drive-in the dopants (form final doping profile) ► ~100 kV voltage is used

17 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Si wafer Aperture Ion source Ion implantation Masked by a SiO 2 pattern

18 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Ion implantation Masked by a SiO 2 pattern It is a low temperature process. Advantage: existing profiles are less effected

19 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Window opening ► With photolithography – always the first step of any patterning ► Problem of oxide steps: step coverage

20 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Patterning: photolithography

21 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET The photolithography E.g. metallization pattern: deposit metal over the entire surface coat with resist UV photography through mask, develop etch off unecessary metal remove resist Photo resist Mask Photo resist oxide window – pattern copied

22 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET A simple pMOS process ► Process at our cleanroom facility ► The process steps

23 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Steps of a simple pMOS process Wafer cleaning

24 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Growth of thick SiO 2 (field oxide) Steps of a simple pMOS process

25 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Photolithography: spin-coating with resist Steps of a simple pMOS process

26 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Photolithography: mask alignment Steps of a simple pMOS process

27 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Photolithography: UV exposure Steps of a simple pMOS process

28 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Photolithography: development Steps of a simple pMOS process

29 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Steps of a simple pMOS process Patterning: oxide etching

30 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Steps of a simple pMOS process Patterning: oxide etching, resist removal

31 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Diffusion from solid boron (pre-diffusion) Steps of a simple pMOS process

32 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Removal of boron glass Steps of a simple pMOS process

33 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Steps of a simple pMOS process Boron diffusion, 2 nd step: driving in (in oxygen)

34 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Photolithography: opening window for thin oxidePhotolithography: removal of rsistGrowth of thin oxide (SiO 2 ) for the gatesPhotolithography: opening contact windowPhotolythography: resist removalDeposition of aluminum Steps of a simple pMOS process

35 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Photolithography: patterning the metallizationWafer with ready chips realizing a simple IC Steps of a simple pMOS process Photolithography: resist removal

36 Budapest University of Technology and Economics Department of Electron Devices Microelectronics BSc course, Technology © András Poppe, Vladimír Székely & László Juhász, BME-EET Steps of a simple pMOS process Dicing, bonding


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