1. CMOS LOGIC STRUCTURE

2. 1.CMOS COMPLEMENTARY LOGIC CMOS is a tech. for constructing IC. CMOS referred to as Complementary Symmetry MOS(COS-MOS) Reason: CMOS uses Complementary & Symmetrical pair of p-type & n-type MOSFET CMOS tech. is used in µp, µc,static RAM & other DLC. CMOS tech. is used for analog ckts such as image sensors, data converters &highly integrated transceivers for many types of commn.

3. Two important char. Of CMOS devices: High noise immunity Low static power consumption Significant power is only drawn while the transistors in the CMOS devices are switching b/w on & off states. CMOS circuitry dissipates less power when static, and is denser than other implementations having the same functionality

4. The main principle advantage behind CMOS ckts that allows them to implement logic gates is the use of p- type and n-type MOSFET to create paths to the o/p form either the voltage source or ground. When the path to o/p is created from the voltage source, the ckt is said to be pulled up. When the path to o/p is created from the gate, the ckt is said to be pulled down.

5. All complementary gates may be designed as ratio less ckts. If all the transistors are the same size the ckt will function correctly. Safety power margin: 1 to 2 volts High voltage CMOS process allows: 15 to 30 volts High density CMOS process allows: 2.5 to 3.5 volts CMOS process has 2 function determining block: n- block & p-block

6. 2.B I CMOS LOGIC BiCMOS: Integration of BJT & CMOS tech. into a single IC. This tech. has commercial appln. In amplifier & discrete component logic design. Most recently it has become the tech. of choice for power electronics products such as voltage regulators.

7. Bipolar transistors offer high speed, high gain, and low o/p resistance, which are excellent prop. For high freq. analog amplifiers. CMOS technology offers high i/p resistance & is excellent for constructing simple, low-power logic gates.

8. 3.P SEUDO N -MOS LOGIC There is another type of active load that is used for nMOS logic, but this load is made from a pMOS transistor. Hence, nMOS logic that uses this load is referred to as Pseudo nMOS logic, since not all of the devices in the ckt will be nMOS(the load will be pMOS).

9. 4.DYNAMIC CMOS LOGIC Dynamic ckts rely on the temporary storage of signal values on the capacitance of high impedance nodes. Requires only N+2 transistors Takes a seq. of precharge and condn. Evaluation phases to realize logic functions. Two phase operation: Precharge ( CLK =0) Evaluate (CLK =1)

10. 5.CMOS DOMINO LOGIC The basic potential problem with the dynamic CMOS logic configuration causes the o/p node to be disconnected from V DD during the evaluation phase, Even if the o/p is also disconnected from GND, the charge of the output node will begin to diminish due to the non-ideal effects of the system.

11. 6.DOMINO ZIPPER LOGIC An alternative to Domino Logic is NORA or Domino Zipper Logic. NORA  ‘NO RAce’ This is another method to eliminate the ‘racing’ problem of directly cascaded dynamic logic blocks. The function of the clocked n-FETs & p-FETs in the pMOS logic stage are reversed compared to the nMOS logic stage. It eliminates the cascading problem, the excess use of pMOS in forming the logic gates reduces the max. clocking speed & increases the surface area of the system.

12. 7. C ASCADE V OLTAGE S WITCH L OGIC (CVSL) CVSL belongs to class of differential logic types The idea is to use a dual n-block instead of a dual p-block & a pair of cross-coupled pMOS transistors compute the logic function & its complement It can be roughly as fast as dynamic logic, it dissipates almost as little static power as static CMOS

13. 8.S OURCE F OLLOWER P ULL - UP L OGIC (SFPL) SFPL is a small variation on pseudo nMOS whereby the load device is an N pull-down & N source follower pull-ups are used on the inputs.(it is useful for high fan-in NOR gates) N pull up transistors can be small limiting i/p capacitance N transistors are also duplicated as pull –down devices in order to improve the fall time Rise time is determined by the P1 inverter pull-up transistor when all inputs are low

14. 9.C OMPLEMENTARY P ASS T RANSISTOR L OGIC (CPL) Utilizes CMOS transmission gate to perform logic Logical i/ps may be applied to both the device gates as well as device source/drain regions Only a limited no. of pass gates may be ganged in series before a clocked pull-up(or pull-down) stage is required If A is high, B is passed through the gate to the o/p If A is high, -B is passed through the gate to the o/p

15. 10.C LOCKED CMOS L OGIC (C 2 MOS) C 2 MOS logic has been used for very low power CMOS and/or for minimizing hot electron effect problems in n-FET devices Clocking transistors allow valid logic o/p only when clk is high Clocking transistors may be at o/p end of logic trees(max performance) or at power supply end of logic tress(max protection from hot electrons)