1. TOPIC : Scan based Design Module 4.3 : Scan architectures and testing UNIT 4 : Design for Testability

2. Introduction There are several forms of scan designs; they differ primarily in how the scan cells are designed. We will illustrate three generic forms of scan design : ◦ Full Serial Integrated Scan ◦ Isolated Serial Scan ◦ Non-serial Scan

3. Full Serial Integrated Scan Architecture Normal sequential circuitFull serial integrated scan circuit

4. Full Serial Integrated Scan The normal parallel-load register R has been replaced by a scan register R s. When N_bar/T = 0 (normal mode), R s operates in the parallel-latch mode; hence both circuits operate the same way. Now Y becomes easily controllable and E easily observable. Hence test generation cost can be drastically reduced.

5. Isolated Serial Scan In this, scan register is in the normal data path. This scan architecture, the selection of the CPs and Ops associated with the scan register R s is left up to the desigener.

6. Full isolated scan If R s is used both to observe and control all the storage cells in S. A test vector y l is scanned (shifted) into R s, loaded into R', and then applied to the circuit C. The response e can be loaded into R', transferred to R s, and then scanned out. The register R s is said to act as a shadow register to R'.

7. Non serial Scan It aim to give full controllability and observability to all storage cells in a circuit. Storage cells are arranged in a random- access bit – addressable memory. During normal operation the storage cells operate in their parallel-load mode. Scan in – appropriate cell is addressed, the data are applied to S in. The output of the cells are wired-OR together. Advantage – Only bits in R that need to changes must be addressed and modified; this saves scanning data through entire register.

8. Non serial Scan Example Random-access scan