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1 Chapter Design For Testability. 2 6.5 The Scan-Path Technique The testing problems with sequential circuit can be overcome by two properties: 1.The.

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Presentation on theme: "1 Chapter Design For Testability. 2 6.5 The Scan-Path Technique The testing problems with sequential circuit can be overcome by two properties: 1.The."— Presentation transcript:

1 1 Chapter Design For Testability

2 2 6.5 The Scan-Path Technique The testing problems with sequential circuit can be overcome by two properties: 1.The circuit can easily be set to any desired internal state. 2.It is easy to find a sequence of input patterns such that the resulting output sequence will indicate the internal state of the circuit. In other words the circuit has a distinguishing sequence.

3 3 The Scan-Path Technique

4 4 Continue The procedure for testing is: 1.Set c=1 to switch the circuit to shift register mode 2.Check operation as a shift register by using scan-in inputs, scan-out output and the clock. 3.Set the initial state of the shift register. 4.Set c=0 to return to normal mode. 5.Apply test input pattern to the combinational logic. 6.Set c=1 to return to shift register mode. 7.Shift out the final state while setting the starting state for the next test. 8.Go to step 4.

5 5 Another Implementation of Scan Path During normal operation: C2 remains at logic 1. C1 is set to logic 0 to latch up data at D1. The output of L1 is latched into L2 when C1 returns to logic 1. Scan in operation: Clocking the test input value at D2 into L1 by setting C2 to logic 0. The output of the L1 latch is clocked into L2 when C2 returns to logic 1.

6 6 6.6 Level-Sensitive Scan Design (LSSD) Clocked Hazard-free Latches

7 7 Level-Sensitive Scan Design (LSSD)

8 8

9 LSSD Design Rules Rule 1: Use hazard-free polarity-hold latches. Rule 2: Latches are controlled by two non-overlapping clocks such that: a) One feeds the other, can not have the same clock b) Gated clock by latch X can not clock latch X

10 10 Level-Sensitive Scan Design (LSSD) Rule 3:

11 11 Level-Sensitive Scan Design (LSSD) Rule 4: Clock primary inputs may not feed the data inputs to latches. Rules 1-4  Level-Sensitive Rule 5: All SRLs must be interconnected into one or more shift registers Rule 6: Sensitizing condition (Shifting)

12 12 Double-latch LSSD

13 13 Single-latch LSSD

14 14 L1/L2* SRL

15 15 L1/L2* SRL

16 16 Continue Advantages of the LSSD Technique 1.The correct operation of the logic network is independent of a.c. characteristics such as clock edge rise time and fall time. 2.Network is combinational in nature as far as test generation and testing is concerned. 3.The elimination of all hazards and races greatly simplifies both test generation and fault simulation.


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