1. EML 4561 Introduction to Electronic Packaging
W. Kinzy Jones, Professor MME
MWF 11:00-11:50
(mobile)
(office)

2. Notes on the field
I am Past President and Fellow, IMAPS, The Microelectronics and Packaging Society
Research in advanced packaging, 1st Level Assembly, Thermal Management, Components and Electronic Materials- Funded over $7MM in past 15 years
Electronic packaging is a application field that crosses over many disciplines. There are 80,000 ME working in the field. Conferences/journals by ASME, IEEE, ASM, IMAPS, etc.
All former graduate student hired prior to graduation!

3. Outline Technological Drivers Design Process Interconnect Technology
Electrical Consideration
Mechanical Constraints
Thermal Management
Material Science Fundamentals
Interconnect Technology
Laminate technology
Ceramic Processes ( thick film, cofire ceramic)
Thin Film Deposited

4. Outline (Cont.) Components Active components technologies
Passive Components technologies
IC Packaging ( from DIP to System-on-package (SOP))
Assembly
First Level Assembly ( wire bonding, flip chip)
Soldering
Manufacturing Processes
Reliability
MIL Standards
Reliability Projections

5. Introduction to Microsystems Packaging

6. Definition of Packaging
Packaging is a Bridge from IC
to System
Board IC
It Controls:
>90% size
Performance
Cost
Reliability

7. Packaging Hierarchy

8. Microsystems Technologies

9. System Packaging Involves Electrical, Mechanical and Materials Technologies

10. Analogy Between Human and Electronics

11. Trend to Convergent Microsystems
Packaging
Photonics
Microelectronics
Discrete Systems RF
Convergent
Microsystems
MEMS
Bioelectronics
Past
Future

12. Building Block of Microsystems Packaging

13. Trend to Convergent Systems
Transistors / chip
WW S/C Revenue ($B)
10000
All businesses, people, objects
Network computing
Wide area / bandwidth
Graphical, voice, multimedia, etc.
Many vendors / platforms
100B
10B
1000 1B
PCs / Servers
Wireless
Wired
Internet
100M
100
10M
Mainframes
Businesses & some people
Client-server computing
Local area connection
Text/graphical interface
Many vendors / few architectures 1M 10
PCs
100K
Businesses
Host-based computing
Mainframe
Dumb terminal
Few vendors / architecture
10K 1 1K
1975
1995
2015
Today
Source: Russ Lange, IBM Microelectronics
Year

14. What are Convergent Microminiaturized Microsystems (CMM)?
Convergent: Two or more functions
Microminiaturized: >1000x volume reductions
Microsystems: systems with micro-scale technologies

15. Trend to Convergent Microminiaturized Systems (CMM)
Functional
Data and Voice
Video
Cell Phone
CONSUMER
ELECTRONICS
Medical Implant/
Diagnostic Monitor/ Communicator
MEDICAL
Technology
Digital, RF, Analog and Optical
Product
Computer, consumer and telecom

16. The Invention of the First IC

17. Moore ’s Law: Doubles Every 18 Months

18. Moore’s Law
Cu - low K
SOC Advances
SiGe
SOI

19. SOC Challenges Integration RF Limits Fundamental Digital Limits
Major Delay Problems
Summary
Fundamental
Design & Verification Complexity
Test Complexity
Process Complexity
Mixed Function Costs
Wafer Fab Costs
Legal Problems
Time-to-market

20. SOC: Integration of Two or More Mixed Functions in a Single IC
(b)

21. What is Wrong with Current Packaging for Tomorrow’s Needs?
Higher Cost
Bulky Size
Cellular Phone
Weight Trend
Active ICs 10%
Passives: 90%
Lower Performance
Poorer Reliability
IC: PPB
Systems Pkg: PPM
Barrier to all future systems

22. What is SOP, SIP, or Board? A.) Today’s Board: Interconnect Components
RF IC
Digital IC
Optical IC
Substrate
A.) Today’s Board: Interconnect Components
Flash
RAM mP IC
Package
Super IC Stack (ASET)
Package (Fujitsu)
Stacked IC (Amkor)
B.) SIP: Stacked Chip/Package for Reduced Form Factors
3-D ICs IC
RF IC
Opto IC
Digital IC RF
Opto
Electrical
Package with Opto, RF, Digital Functions
C.) SOP: Optimizes Functions Between ICs and Package

23. What are SOC, SIP, and SOP? SOC: System on Chip SIP: System in Package
Highly integrated and mixed signal IC with partial system functions in one component
SIP: System in Package
3-D IC or Package Assembly
Requires Systems Board
SOP: System on Package
Microminiaturized system-level board with two or more embedded RF, digital, analog and optical functions
Best of on-chip and package integration for cost, performance, size and reliability
Similar to SOC but total system function in a microminiaturized board

24. SOP: SIP + SOC+Systems Board
3 -D Stacking of ICS or Package Structures, Similar to PWB
Macro dimensions
Vertical stack up
Testable
3 -D Build up, similar to IC Fabrication
Micro to Nano dimensions
Sequential build up and test similar to MCM-D and IC
Wafer to IC concept for high yield
MEMS
Ga-As
SIP
SOC
SOC
MEMS
Ga-As
SIP

25. Why SOP?
SOC is complex to design and test, expensive to Fabricate, long time-to-market and presents fundamental limits.
IC company’s dream for decades. No complete system has been shipped to date.
SOP optimizes the best of IC and package integration for cost, performance, size and reliability.
Faster turn-around and faster time-to-market.
Provides full system solution today that SOC provides tomorrow.
SIP is a 3-D IC or package, not a complete system

26. Information Technology is a Trillion $ Industry Microsystems & Packaging is 25% of IT
Industrial &
Medical
11%
$105B
Automotive 5%
$ 48B
Military 9%
$ 8.7B
Consumer
26%
$112B
Business Equip
38%
$ 383B
Communications
26%
$ 259B
Source: Prismark

27. MSP Market ($320 B) Opto & MEMS ($30B) Microelectronics ($165B)
Systems Packaging ($125B)

28. Information Technology and Microsystem Markets
Billion $/Year

29. Hardware and Software Markets

30. Functions of Packaging

31. Package Interconnections

32. System Level Packaging
Core Technologies
Substrates, circuit boards
Interconnect
Passive components
Active components
Packaging
Traditionally these were treated as discrete elements
Advanced applications require integrated approach of
System Level Packaging

33. Substrates and Circuit Boards
Printed Circuit Board (PCB), Printed Wiring Board (PWB)
Epoxy-glass composite, copper
FR-4, FR = fire retardant
Advanced Resins
Polyimide
BT = bismaleimide traizine
CE = cyanate ester
Ceramic substrates
Aluminum oxide, aluminum nitride, beryllium oxide, glass-ceramic
Interconnect metals - W, Mo, Au, Cu, Ag
Multichip Modules
MCM-D,C,L
Platform
Support interconnect and components
Thermal path away from ICs
Withstand mechanical stresses and vibrations

34. Packaging Evolution ?

35. Microelectronic Density Trends
microprocessors
logic

36. Rent’s Rule

37. Packaging Evolution

38. I/O Density Trends
Chip

39. Package Evolution

40. Packaging Trends (Cont.)

41. Assembly Processes Board Fabrication Populating the board Soldering
Single layer
Multilayer
PCB
Flex
Ceramic
Populating the board
Pick and place
Insertion
Die attach
Soldering
Solder paste reflow
Wave solder
Solder bump reflow
Encapsulation

42. SIA Roadmap for Chip Interconnections, 1995

43. CMOS Device Trends
Buda et al, 42 CPMT, pp36-41, 1992

44. NEMI Roadmap, 1996 Packaging trends in Consumer Electronics
Packaging trends in Automotive Electronics

45. iNEMI Roadmap, 2009

46. NEMI Roadmap for Packaging Trends in High-Performance Systems

47. High Performance Systems, iNEMI 2009

48. Interconnect Density, Std. PWB
.1mm = 4 mils

49. Thermal Cooling Requirements

50. Types of First Level Packages

51. Chip-Scale Packages

52. Types of Ball Grid Arrays

53. Flip Chip Assembly Chip Substrate
Example- Controlled Collapse Chip Connection-C4 (IBM)
assembly on ceramic substrate

54. Solder Primary functions
Electrical connection between component and interconnect
Mechanical attachment of component to board
Thermal path from component to board
Alloys of various compositions and melting points
Lead-Tin solder most common
Eutectic composition: 63% Tin, 47% Lead
60/40 or 2% silver added
Solder paste for screen printing, pressure dispensing
Alloy particles
Flux and activator chemicals
Vehicle to control viscosity
Wave soldering
Foam or spray flux
Preheat board
Turbulent wave to spread solder
Laminar wave to smooth

55. Effect of Underfill on Temp Cycling Performance
With filler, 27ppm

56. Functions of a Multichip Package

57. Illustrations of MCM Types

58. Low Temperature Cofired Ceramics with Buried Components

59. Packaging Efficiency

60. Packaging Considerations that Effect the Electrical Performance

61. Interconnects Worsen:
Signal Integrity
Performance: switching, speed
Reliability
Form, fit, and function- weight, volume, power

62. Interconnects Can Have Very Important Electrical Properties
Property
Self-inductance
Capacitance to ground
transmission line
Mutual Inductance, capacitance
Resistance, loss
Possible Impact
Ground bounce
Delay, power sag
Propagation delay, reflection
Cross-talk, noise
Damping, ringing, power sag

63. Drivers for Reduction of Interconnect Length
Directly reduces inductance, capacitance, resistance and delay
Indirectly reduces switching time, power, size, ringing, ground bounce, and power sag

64. Electrical Fundamentals
Resistance ( ohms). Relates Ohms law relationship between current and voltage, V=IR. Resistivity, , is a materials property, in ohm-meters. Resistance, R = Length x  / cross-sectional area of conductor
Capacitance (farads) relates to the ability to store charge. Capacitance for a parallel plate capacitor is proportional to the dielectric constant,K, times the area of the plate/ thickness of dielectric.
Inductance ( henry)- relates to the voltage generated to oppose a change in current

65. Basic Resistance Equation
Resistance R = L / A = L  /wt = L/w Rs where Rs is defined as the sheet resistivity,  is resistivity, L is the length and A is the cross sectional area of the conductor/resistor
A square ( L=W ) for a fixed thickness of material has a fixed resistance per square, independent of size. A square anything

66. Capacitance is In the insulation between more than one conductor
Orders of Magnitude higher outside the chip than inside
The dominate determinant of digital speed

67. Dielectric Constants of Some Insulators

68. Capacitance of Electrically Short Interconnections
Capacitance is the sum of all output capacitance of all drivers to that interconnect, the input capacitance of all receivers, and the distributed capacitance to ground of the interconnection

69. Switching Time, Power
If a step voltage is applied to an RC network, the time delay is proportional to RC. If the capacitor is charged from zero to full charge, the energy dissipated, W, is independent of R and equals CV2/2. But energy is also power X time delay. If we operate twice as fast, the circuit will dissipate twice the power.

70. Inductance
Opposes a change in current by generating a back voltage. If the current change is positive, the back voltage subtracts from the voltage applied, causing a power sag.
The voltage is equal to the inductance times the rate of change of the current , VL= L di/dt
Self inductance exists in every wire, trace, wire bond, solder joint, etc..It is minimized by large, short conductors, or a sheet conductor as a ground or power plane.
Example: If we switch 1 amp in 5 nsec on a 1” trace with 7.8 nH, we generate a back voltage of 1.6 volts.

71. Crosstalk
There is a mutual capacitance between two adjacent insulated conductors that couples a fraction of one voltage to the other
There is also mutual inductance, functioning as a transformer by generating a voltage in each when the current changes in the other.
This is crosstalk. Can be minimized by design (keep talkers and listeners apart) and use of ground/power traces between talkers/listeners

72. Ground Bounce, Power Sag
Cause: Common-mode impedance, usually inductive
Digital devices require most of their power supply current during switching. Clocked signals switch together, so there could be a large total surge
The inductance in the power and ground leads causes ground bounce and power sag.

73. Bypass ( decoupling) Capacitors
To reduce power sag and ground bounce, add decoupling capacitors. Value should be nF/sq.cm of silicon. Decoupling capacitors should have low parasitic inductance.
Capacitors serve as local energy reserves and need to be close to the power/ground leads

74. RLC Circuit Switching
The voltage step sent down an interconnect can be distorted badly by the R, C, and L on the interconnect
This distortion can be removed by the right balance of the values of R,L and C. When R = 2* sqrt(L/C), critical damping occurs
If R is above critical damping, switching slows down; if below, ringing of the signal occurs

75. Critical Damping

76. Transmission Lines
Any interconnect whose length is over a small fraction of the wavelength of the signal it carries acts like both a transmission line and an antenna radiating or receiving noise
As speed increase, the lumped analysis of L,R,and C components must be replaced by the distributed network of L,R, and C.
Property shielded interconnects minimize the effect of antenna properties, but the transmission properties remain

77. Transmission Line Properties
A transmission line appears as a string of small inductors and capacitors, with seven principal properties:
length L, inductance per unit length, capacitance per unit length, impedance (Z), attenuation, propagation velocity, and time delay

78. Transmission Line Equations

79. Transmission line traces
Matched impedance systems require containment of the electrical fields. This has lead to designs including the stripline, the microstrip, the buried microstrip. Additionally, for multilayer routing, vias must be considered
Stripline microstrip

80. Microstrip Design for 50 Impedance

81. Traveling Waves on an Infinite Line
Switching on a DC source voltage, V, :
draws the same current as a resistor of value Zo connected to V.
current flows down the line at the propagation velocity, while the current progressively charges up the line capacitance to voltage V. Hence a voltage step V also travels down the line.
Draws current indefinitely due to an infinitely long line
The source only sees a resistive load Zo continuously drawing current

82. Traveling Waves on an Unterminated Line
When the line is unterminated ( R is infinite):
Kirchoff’s current law still applies at the far end: the sum of current entering the end must equal the current leaving the end. But there is no load to draw current from the end node.
Therefore, an equal reflected current wave is generated that travels back toward the source.
This reflected current wave requires an extra voltage source, V, to propel it, so the voltage at the far end steps up to 2V.
This increased voltage travels back towards the source along with the reflected current.
What happens at the source depends on the source’s internal impedance
The waves can on occasion reflected back and forth several times

83. Lines Traveling Waves Capacitively Terminated
The problem of reflection is compounded by capacitance at the ends.
When a transmission line drives a capacitor, the extra capacitance causes:
reflections, since the line is now mismatched
ringing for some drivers, since there is no longer critical damping
CMOS inputs are essentially capacitive.

84. AC Termination
To minimize power dissipation, a series capacitor,C, can be added to the terminating resistor
This terminated the line only when a voltage transition occurs and allows no DC power dissipation in R
The value of C must be selected carefully, either by simulation or experimentation to minimize the effect of capacitively terminated lines.

85. When Interconnections are Electrically Significant
When interconnects degrade switching time
When the signals are not correctly damped
When large amounts of current switch
In the time domain, when the line propagation delay approaches the driver switching time. Propagation delay is proportional to length
In the frequency domain, when the wavelength of the signal ( including harmonics) are not long compared to the length of the interconnect ( for 100 Mhz- over a few centimeters)

86. Packaging What packaging provides:
Interconnection
Power Distribution
Thermal Management
Environmental Protection
What the package is made from--materials, parts
What is used to design and fabricate packages:
Facilities and Equipment
Manufacturing and Design Tools
Process by which the package is produced over time

87. Technology Drives
Increases in semiconductor complexity from decreased feature size
Corresponding increases in systems speed
Increase in input/output (I/O) density
Increase in power density (W/cm2)

88. Levels of Packaging 1st Level Connection 2nd Level Connection
IC to Common Circuit Base
Wirebonds or solder bumps to package base
2nd Level Connection
Common Circuit Base to Circuit Board
Package leads soldered to PCB
3rd Level Connection
Assembly of multiple boards into larger assembly
Video card, modem, game port on a PC motherboard
4th and 5th Level Connections
System level assembly with several 3rd Level subassemblies
Motion control, visual alignment, user interface, etc. in manufacturing equipment