# ECEN 5004 – Digital Packaging Chapter 4 “Fundamentals of Electrical Package Design” Objectives: Introduction to electrical package design Signal integrity,

## Presentation on theme: "ECEN 5004 – Digital Packaging Chapter 4 “Fundamentals of Electrical Package Design” Objectives: Introduction to electrical package design Signal integrity,"— Presentation transcript:

ECEN 5004 – Digital Packaging Chapter 4 “Fundamentals of Electrical Package Design” Objectives: Introduction to electrical package design Signal integrity, power/grounding system, EMI Basic equations for calculating design parameters Major design tasks: Creating a signal distribution system Creating a power/grounding system Overcoming parasitic reactances an obstacle

ECEN 5004 – Digital Packaging 4.1 What is Electrical Package Design? Electrical signal and power path design Functions: Provide signal/power distribution Protection from environment (chemical/ physical) Thermal mitigation Connectivity within package, between layers Potential for lumped passive elements

ECEN 5004 – Digital Packaging 4.1 What is Electrical Package Design?

ECEN 5004 – Digital Packaging 4.2 Fundamentals of Electrical Design Ohm’s Law Minimize resistances to minimize thermal losses Skin Effect AC resistances are higher than DC, particularly at elevated frequencies where current concentration is highest at the surface Capacitances and Inductances act as storage elements Kirchhoff’s Laws (KVL/KCL) Voltages around a loop sum to zero Currents into a node sum to zero Useful for calculating voltages and currents throughout the packaged circuit

ECEN 5004 – Digital Packaging 4.2 Fundamentals of Electrical Design Noise Undesired signals affect circuit operation Minimize unwanted internal/external interference Parasitic capacitances/inductances are problematic Minimize copper-conductor lengths to reduce parasitics Time Delay Resistance + capacitance or inductance = delay (T=RC, T=L/R) RC delay limits overall speed of the packaged system Contributes to simultaneous switching noise (ssn) Simultaneous Switching Noise (ssn) Fluctuation in signals resulting from transient variation in supply voltages Caused by the limited ability of the supply to quickly respond Use decoupling capacitors to provide instantaneous energy

ECEN 5004 – Digital Packaging 4.2 Fundamentals of Electrical Design Transmission Lines Electricity carried by EM waves Finite signal propagation due to material properties (condensed matter physics) Proper ‘matching’ required for no reflections Crosstalk Results from capacitive/inductive coupling Transmission line modeling to mitigate effects EMI Time-varying signals and external noise Switching power supplies Proper grounding

ECEN 5004 – Digital Packaging 4.2 Fundamentals of Electrical Design SPICE Modeling Usually a nightmare for complex circuits Dreaded ‘floating node’ and ‘infinite current loop’ errors Limited to 64 nodes in pSPICE version 9.2 Otherwise useful for general analysis

ECEN 5004 – Digital Packaging 4.3 Electrical Anatomy of Packaging Dealing with parasitic elements They’re everywhere you don’t want them to be Cause delay, skew, lead/lag, and transient power fluctuations Transmitted signal winds up being degraded Primary challenge: Handling non-ideal effects Package design must meet specifications

ECEN 5004 – Digital Packaging 4.3 Electrical Anatomy of Packaging

ECEN 5004 – Digital Packaging 4.4 Signal Distribution Devices and Interconnections MOSFETs are most frequent devices Operated as a switch (cutoff / saturation modes) Binary state at the gate determines mode * Diagrams conveniently stolen from Wikipedia

ECEN 5004 – Digital Packaging 4.4 Signal Distribution Non-idealities in MOSFETs On-resistance R ON Leads to non-zero voltage drop Thermal losses Potential for other parasitic problems and delays Switching delay, rise/fall times Limit speed of packaged circuit Consume energy to charge/discharge gate capacitance Capacitive Delay of Interconnections

ECEN 5004 – Digital Packaging 4.4 Signal Distribution Kirchhoff’s Laws and Transit Time Delay Propagation at C (3 x 10 8 m/s) in air Propagation at { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/14/4361814/slides/slide_12.jpg", "name": "ECEN 5004 – Digital Packaging 4.4 Signal Distribution Kirchhoff’s Laws and Transit Time Delay Propagation at C (3 x 10 8 m/s) in air Propagation at

ECEN 5004 – Digital Packaging 4.4 Signal Distribution Transmission Line Behavior of Interconnections LΔz is total series inductance of equivalent circuit RΔz is total series resistance of equivalent circuit Application of Kirchoff results in Figure 4.9 See ‘Telegrapher’s Equations’ for further information

ECEN 5004 – Digital Packaging 4.4 Signal Distribution Waves Between Digital Gates Parallel strip is common, easy to design Microstrip, embedded microstrip, and stripline Microstrip: between air and dielectric E-Microstrip: embedded within a dielectric Stripline: connection between two metal layers

ECEN 5004 – Digital Packaging 4.4 Signal Distribution Signals exhibit a finite velocity Output from line is not instantaneous v p = 1/(LC) 1/2 Input appears to be a resistance (top figure) Load terminated by MOSFET (high resistance) Equivalent circuit at (a) generator and (b) load

ECEN 5004 – Digital Packaging 4.4 Signal Distribution Match the Terminations and Line Impedances Basic Electromagnetics Unmatched terminations lead to reflections How to match previous figure: (a) Matching by adding 45 ohm series resistance, and (b) Resulting system with matched impedances.

ECEN 5004 – Digital Packaging 4.5 Power Distribution Interconnects must also carry power Active elements require power to operation Voltage drop and inductive effects are main issues Supply voltage may not be the same everywhere due to V=IR drops throughout the package Parasitic inductance leads to voltage drops: V supply = (L 1 +L 2 )(di/dt)+R*i(t) V load (t) = V supply (1-e -t/T )u(t) The load voltage is therefore the supply voltage plus the induced time constant parameter

ECEN 5004 – Digital Packaging 4.5 Power Distribution Effective power distribution inductances Inductances L1 and L2 are for voltage and ground leads for the package Power distribution inductance Inductive effect

ECEN 5004 – Digital Packaging 4.5 Power Distribution Effective Inductance Used to evaluate the power distribution performance of the package Contribution can be either additive or subtractive Additive: currents are in same direction Subtractive: currents are in opposite directions Assuming a mutual inductance M between inductors: V supply = (L 1 +L 2 -2M)(di/dt)+Ri(t) Time Constant: T = (L 1 +L 2 -2M)/R Effective Inductance: L eff = L 1 +L 2 +M (reduced due to mutual inductance between voltage and ground leads of the package)

ECEN 5004 – Digital Packaging 4.5 Power Distribution Power Supply Noise Local, real supplies source finite current With series inductances, the local Vdd will drop since the inductor current cannot change instantaneously Result: transient fluctuations in supply voltage ΔV = L eff (dI/dt) Called simultaneous switching noise (ssn) Effect of Packaging on Inductance Minimizing inductance reduces supply noise Effective inductance varies from package to package (quad flat pack, QFP, or ball grid arrays, BGAs, etc.) Inductance is either due to spheres or planes

ECEN 5004 – Digital Packaging 4.5 Power Distribution Inductance and Noise Relationships With series inductances, the local Vdd will drop since the inductor current cannot change instantaneously Result: transient fluctuations in supply voltage ΔV = L eff (dI/dt) Called simultaneous switching noise (ssn) Effect of Packaging on Inductance Minimizing inductance reduces supply noise Effective inductance varies from package to package (quad flat pack, QFP, or ball grid arrays, BGAs, etc.) Inductance is either due to spheres or planes

Download ppt "ECEN 5004 – Digital Packaging Chapter 4 “Fundamentals of Electrical Package Design” Objectives: Introduction to electrical package design Signal integrity,"

Similar presentations