1. Chapter 5 Larger combinational system

2. Contents Delay in combinational logic circuit
Analysis of combinational circuits
Design of combinational circuits
Some common types of circuits: adders(加法器), decoder(译码器), encoder(解码器) an priority encoder, multiplexer(数选器)
Gate array: ROM, PLA, PAL

3. Delay in combinational logic circuits
Consider the effect of the delay through gates
Delay in combinational logic circuits
When the input to a gate changes, the output of that gate does not change instantaneously(即刻); but, there is a small delay, Δ. If the output of one gate is used as the input to another, the delays add.

4. a hazard or a glitch Figure 5.1 No small delay, Δ.B C X F A B C
No small delay, Δ. 1Δ 2Δ X F A B C
There is a small delay, Δ. X
a hazard or a glitch F

5. 4.1.1 Analysis of Combinational Circuits
组合电路分析
This section will present the analysis process of digital circuits and examples .
Analysis is a procedure from a logic circuit to function descriptions.
Purpose: Analysis is used to determine the behavior of a logical circuit , to verify that the behavior of a circuit matches its specification; or to assist in converting the circuit to a different form，either to reduce the number of gates or to realize it with different elements.

6. Step 1: Write out the algebraic expression of a logic circuit.
Step 2: Formalize the truth table .
Step 3: Describe the function or behavior of a logic circuit.
Example 4.1: Find a simplified switching expression and circuit for network of Fig 4.1
Fig 4.1.

7. Fig 4.1
Analysis:

8. Example 4.3: Analyze the function of Fig. 4.0.4.
1. Write out the algebraic expression
Fig
2. Formalize the truth table
A1 A0 F
m d0
m d1
m d2
m d3
3. The function of this logic diagram

9. The three steps of analysis are listed as follows:
Step 1: Write out the algebraic expression of a logic circuit.
Step 2: Formalize the truth table .
Step 3: Describe the function or behavior of a logic circuit.

10. Example 4.2: analyze behaviors of Fig. 4.0.3.
and-or-not gate

11. Example 4.2: analyze behaviors of Fig. 4.0.3.
a b c
Cout S
0 0
0 1
1 0
1 1
1. Write out the algebraic expression
2. Formalize the truth table
3. Describe the function or
behavior of a logic circuit
1-bit full adder ai bi ci Si
Ci+1
Full
Adder

12. 4.1 Design (Synthesis) of Combinational Circuits 组合电路设计（综合）
This section will present the design process of digital circuits and examples.
Digital circuits are designed by transforming a word descriptions of function into a set of logic equations and then realizing the equations with logic elements.
The design process for combinational circuits is shown as follows : (see P17-19)
1: Represent each of the inputs and outputs in variable.
2: Formalize the design specification either in the form
of truth table or of algebraic expressions.
3: Simplify the description (algebraic expressions) in
terms of gates .
4: Implement the circuits with components.

13. (1) showing the truth table (2) simplifying logic expression
Example : Design a full subtracter, that is a circuit which computes a-b-c, where c is the borrow from the next less significant digit and produces a difference , D, and a borrow, P from the next more significant bit. (P275 Solved Problems 1.)  
Solution 1:
(1) showing the truth table
(2) simplifying logic expression
(3) drawing the logic circuit
(1) the truth table
a b c D P
 (2) logic expression
D=a’b’c+a’bc’+ab’c’+abc
P=a’b’c+a’bc’+bc

14. ? (3) logic circuit D=a’b’c+a’bc’+ab’c’+abc P=a’b’c+a’bc’+bc
 (2) logic expression
D=a’b’c+a’bc’+ab’c’+abc
P=a’b’c+a’bc’+bc
(3) logic circuit ?

15. Solution 2: D=a’b’c+a’bc’+ab’c’+abc P=a’b’c+a’bc’+bc
P66 use NAND express NOT

16. Example 4.1.2 Blood type detect
A B
C D F 说明
0 0
0 1
1 0
1 1 1
O→O
O→A
O→B
O→AB
A禁送O
A→A
A禁送B
A→AB
B禁送O
B禁送A
B→B
B→AB
AB禁送O
AB禁送A
AB禁送B
AB→AB
表 真值表
1.Formalize the truth table

17. 00 01 11 10 1 CD AB 2.From truth table to k-map
图3-8输血、受血卡诺图 1
3.Write the logic expression

18. 4. Draw the logic circuit

19. Analyze the function for each of following circuits.
Exercise :
Analyze the function for each of following circuits. A B F1 F2
& 1

20. The classification of digit elements (components): 1: SSI (small scale integration)—gates 2: MSI (medium scale integration)—single function module such as Adder, Decode, Encode, Multiplexer Comparator, ROM,PLA,PAL ,Counter , shift-register 3: LSI (large scale integration)—some functions or small system 4: VLSI (very large scale integration)—a system

21. 4.2 Adders (加法器） 4-bits adder integrated（4位加法器） SUM Carry out
Attention : CI0=0

22. Example 4.2.1: use of 4-bits adders to realize a 8-bits adder .

23. Example 4.2.2: Design a 4-bits subtracter using 4-bits adders and gates to realize it .
From section ,we knew that (A-B) is computed as (A+(-B)) , thus we take the bit by bit complement of B and then add. The logic circuit is shown as following . S 3 CO A B CI Σ 2 1

24. Example 4.2.3: Design an adder to add two decimal digits (plus a carry in), where the digits are stored in 8421 code .(Assume that none of the unused combinations of input variables ever occur.) The output is the code for a decimal digit plus the carry out. (see P276)
Sum<=
No correction

25. The logic design for S.P.2 cin A B 4-Bit Adder c Carry detect
4-Bit Adder
Cout
sum

26. Carry Detect logic design

27. 4.3 Decoders (译码器)
A Decoder is device that, when activated, selects one of several output lines, based on a coded input signal. Most commonly, the input is an n-bit binary number, and there are output lines.
example: a two-input (four output) decoder a b 1 2 3
The output is active high

28. 4.3 Decoders (译码器)
Most decoders also have one or more enable inputs. When it is inactive, all of the outputs of the decoder are inactive. In most systems with a single enable input, that input is active low.
En’ a b 1 2 3 X a 1 b 2 3
En’

29. (3-to-8 decoder with 3 input lines and 8 output lines)
4.3.1
1 . The function table of the decoder
(3-to-8 decoder with 3 input lines and 8 output lines)
En1En2’En3’ C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 x x x x x
x 1 x x x x
x x x x x
active low Outputs
输出低电平有效
enable inputs
EN1=1
EN2’=0
EN3’=0
Address inputs

30. 74138 logic circuit

31. The pin connection and symbol of 741382 3 4 5 7 6 A B C S2 S3
GND S1
Vcc Y0 Y1 Y2 Y3 Y5 Y4 8 16 15 14 13 12 10 11 9 Y7 Y6
74138

32. There are many commercial decoder chips as follows:
Notice :The n-to-2n decoder is called full decoder.
In order to understand more about active low output , the example of logic simulation of 2-to-4 decoder is presented.
4-to-16 decoder
2-to-4decoder

33. 4.3.1
2.BCD to decimal decoder
BCD code Decimal digits DCBA
Active high outputs

34. BCD to Decimal decoder implement
1.Formalize the truth table (omit).
2. Draw K-map AB
3. Algebra expression
0=A’B’C’D’ =A’B’C’D
2=B’CD’ =B’CD
4=BC’D’ =BC’D
6=BCD’ =BCD
8=AD’ =AD CD 4 X 8 1 5 9 3 7 2 6 00 01 11 10
4.Draw the logic circuit.(略)

35. 3.Display Decoder (see P261)
4.3.1
3.Display Decoder (see P261)
Digital watches and other electronic equipment often display BCD-encoded decimal digits on seven-segment displays. (七段数码显示管）
a b c d e f g
Z Y X W a b c d e f g
Decimal DCB code Display Segment
digit WXYZ a b c d e f g
BCD seven-segment
decoder

36. 4.3.2 Decode application 译码器应用
A common use of the enable function of a decoder is to extend the decoding capability by allowing multiple decoders .
Example 4.3.1: use of 3-to-8 decoders to realize 4-to-16 decoder. (active low outputs)
3-8 decoder: input output-8
4-16 decoder: input output-16
74138 is a 3-8 decoder, which has one active high enable and two active low enable. We have to use these enable signals to realize 4-16 decoder.

37. a b c d Y Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
Y10
Y11
Y12
Y13
Y14
Y15
4-16 Decoder
Functional Table

38. 4.3.2 Decoder applications Address Decoding (地址译码)
Example 4.3.2: Find the addresses of Y0~Y7 as shown in Fig.4.3 .
Fig.4.3
To make running, F1=1, and A3=0, and F2=0.
F1=A5A7=1 => A5=A7=1
F2=A4+A6=0 => A4=A6=0
A7 A6 A5 A4 A3 A2 A1 A0
x x x F1 F2
Addresses are:
( )2~( )2
or (A0H ~ A7H)

39. 4.3.2 Decoder applications (con.)
Implement the logic functions using decoder and gates.
Each active high output of a decoder corresponds to a minterm of that function, thus all we need is an OR gate connect to appropriate outputs.
With an active low output decoder, the OR gate is replaced by a NAND (making a NAND-NAND circuit from an AND-OR).

40. This is minterm Active high output 3-8 decoder truth table
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Y0=A’B’C’
Y1=A’B’C
Y2=A’BC’
Y3=A’BC
Y4=AB’C’
Y5=AB’C’
Y6=ABC’
Y7=ABC

41. realize the following functions using a 74138 decoder and gates
For example:
realize the following functions using a decoder and gates
WHY?

42. Example : Write the expression
f(a,b,c)= ∑m(1,2,3,4,5)
=a’b’c+a’bc’+a’bc+ab’c’+ab’c
=m1+m2+m3+m4+m5
f ’(a,b,c)= ∑m(0,6,7)
=m0+m6+m7
M0=a+b+c
m0=a’b’c’
m0’=(a’b’c’)’
=a+b+c
=M0
Mi=mi’ 1
111
110
101
100
011
010
001
000 f’ f
abc
f=(f ’)’=(m0+m6+m7)
=m0’m6’m7’
=M0M6M7
=(a+b+c)(a’+b’+c)(a’+b’+c’)
∑m(1,2,3,4,5)= M0M6M7

43. Example 4.3.4: realize the following functions using a 74138 decoder and gates:
Example 4.3.5: design 1-bit full adder using a decoder and gates.
There are three examples in P279-4,P280-5 and P281-6

44. 4.4 Encoders and Priority Encoders (编码器和优先编码器)
An encoder is the inverse of a decoder. A decoder’s output code normally has more bits than its input code. If the device’s output code has fewer bits than the input code, the device is usually called an encoder.
For example, use NAND gate to implement 8-3 encoder

45. 真值表

46. 8-3 encoder logic circuitF3 F2 F1
&
&
& I1 I2 I3 I4 I5 I6 I7 I8
8-3 encoder logic circuit

47. 4.4 Encoders and Priority Encoders (编码器和优先编码器)
If more than input can occur at the same time, then some priority must be established. The output would then indicate the number of the highest priority device with an active input. The priorities are normally arranged in descending (or ascending).
The truth table for an eight-input priority encoder is shown in page 244, table 4.6.

48. For example: SP7
Design a priority encoder with four active high inputs 0,1,2 and 3, and three active high outputs, A and B indicating the number of the highest priority device requesting service, and N, indicating no active requests. Input 0 is the highest priority ( and the 3 is the lowest).

49. 4.5 Multiplexers (Data Selectors) P245 多路数据选择器
A multiplexer is basically a switch that passes one of its data inputs through to the output, as a function of a set of select inputs. Often, sets of multiplexers are used to choose among several multi bit input numbers.
数据选择器实质上是一个开关，作为一组选择输入的函数，它让某一路输入数据通过，到达输出。经常使用一组数据选择器，从几个多位输入数字中进行选择。

50. 1. Write out the algebraic expression
Recall: the combination logic analysis
1. Write out the algebraic expression .
2. Formalize the truth table
A1 A0 F
m d0
m d1
m d2
m d3
3. The function of this logic diagram
Multiplexers

51. 4.5 Multiplexers (Data Selectors) P245 多路数据选择器
The function table of a Multiplexer
(4-to-1 Multiplexer ) (4选1 数选器)
a 4-way Multiplexer
Select
inputs
Data inputs
active low
Enable input
output
function table
En’ S1S0 Y
1 x x D0 D1 D2 D3

52. In general, a multiplexer (also called data selector) is a modular device that selects one of many input lines to appear on a single output line.
En’ S1S0 Y
1 x x D0 D1 D2 D3 D0 D1 D2 D3 Y
S1S0
From the function table we may write
The selection input code forms the minterms of two variable, S1 and S0. Hence,we may write

53. There are many commercial MUX chips as follow:
8-to-1 MUX two (dual) 4-to-1 MUX
four (qual) two-way MUX (2-to-1MUX)

54. 4.5.2 Extending the multiplexer capability
A3 A2 A1 A0 Y D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
D10
D11
D12
D13
D14
D15
Example 4.5.1: use of 4-to-1 MUX
to realize 16-to-1 MUX. ?
Solutions:
1. Using A3 and A2 to control four 4-1 MUXs’ enables
2. Using A3 and A2 to control four 4-1 MUXs’ outputs

55. Solution 1:decoding to extend
D0 D1 D2 D3
D4 D5 D6 D7
D8 D9 D10 D11
D12 D13 D14 D15

56. Solution 2: selecting to extend
D0 D1 D2 D3
D4 D5 D6 D7
D8 D9 D10 D11
D12 D13 D14 D15

57. MUX applications
Implement the logic functions using MUX and gates.
The expression of 4-to-1 MUX
(1)
The expression of a logic function
(2)
As compared (1) with (2) , we can consider A , B and C as S1 , S0 and Di. We can write
S1=A 、 S0=B
D0=C’、 D1=C 、D2=C 、 D3=C’
Can you design a circuit for F using 4-to-1 MUX as above?

58. Example 4.5.2: realize the following functions using a 8-to-1 MUX and a 4-to-1 MUX separately.B C 1 F F’
From the function of F, we know that there are 3 variables, (ABC).
A 8-to-1 MUX has 3 select inputs, and a 4-to-1 MUX has 2.
Case 1. Variable select inputs, then data inputs =0 or 1
Select 8-to-1 MUX, we have

59. Case 2. Variable > select inputs, then 1 Y D 2 3
EN'
4-to-1 F B A C
Gnd
Case 2. Variable > select inputs, then
data inputs = variable or function
Select 4-to-1 MUX, we have
We have to make 2 variables of ABC become the select inputs of 4-to-1 MUX. Here we select AB=A1A0, thus

60. For example
We have four 3-bit numbers, w2—w0, x2—x0, y2—y0, and z2—z0. We want to select one of these, based on the input s and t( where st=00 selects w, st=01 selects x and so forth). The answer is to appear on output lines f2—f0.
1.use a multiplexer chip to do this.
2. Use 4-1 multiplexer to do this.
现有4个3位的数字, w2—w0, x2—x0, y2—y0, and z2—z0. 需要从中选择一组, 条件是基于输入s 和 t(当st=00时选择w一组，当st=01时选择x一组，依次类推）。选择的答案显示在一组输出线路上 f2—f0.
1）使用4选一数据选择器完成该功能
2）请使用74153 芯片完成该功能。

61. 4.6 Three-state gates and open-collector gates 三态门和集电极开路门（OC）
So far, we never connected the output of one gate to the output of another gate, since if the two gates were producing opposite values, there would be a conflict. There is a real possibility that one or more of the gates would be destroyed .
There are two design techniques that have been used that do allow us to connect outputs to each other .They are referred as three-state (or tristate) output gates and open-collector(集电极开路) (or OC) gates.
This is dangerous!

62. 4.6.1 Three-state gates （三态门）
In a three-state gate ,there is an enable input, shown on the side of the gate. If that input is active (it could be active high or active low), the gate behaves as usual. If the control input is inactive, the output behaves as if it is not connected (as an open circuit 开路).
active low enable
active high enable a f EN
Three state
buffer
EN a f
1 x Z
EN a f
0 x Z

63. Three state outputs also exist on other more complex gates as follow .
Three-state AND gate
Three-state NAND gate
Three-state
NOT gate

64. The applications of three-state gates
Realizing a 2-to-1 MUX or wired OR(线或)
2-to-1MUX
e F
0 b
1 a
Wired-OR
F=ae+be’
Question
F=?

65. Three-state used for Bus
CPU 10 01 00
Display
Printer
Keys
A bus is a set of lines over which data is transferred. The bus itself is really just a set of multiplexers.

66. 4.7 Gate arrays—ROMs, PLAs and PALs
The basic concept on Gate arrays(门阵列)
Gate arrays are one approach to the rapid implementation of fairly complex systems . They come in several varieties , but all have much in common .The basic structures are illustrated as follow .
AND arrays
OR arrays

67. Two structures simplified for array gates are shown .
A “x” or a dots is represented a connection. Please see example 4.5
There are three common types of combinational logic arrays.
We will discuss them in more detail in the sections later .

68. 4. 7. 2 ROM(只读存储器） In a read-only memory (ROM), the AND array is fixed
ROM(只读存储器） In a read-only memory (ROM), the AND array is fixed. It is just a decoder, consisting of 2n AND gates .The user can only specify the connections to the OR array. Thus, it produces a sum of minterms. A ROM has one AND gate for each minterm.
Example: F and G functions implemented with ROM is
shown right.
F=A’B’+A’B+AB
G=A’B’+AB’ F G A
A'B'
A'B
AB' AB B

69. ROM technologies PROM -- programmable read-only memory(可编程ROM)
The user can enter the connections using a special programming device（编程器）.
Unfortunately, ROMs and PROMs can’t be altered once they are programmed. They must be discarded .
EPROM--erasable programmable read-only memory
The EPROM is programmed by using a special programming device. The EPROM may then be reprogrammed with new information. However, it can be quickly dissipated by irradiating the chip with an ultraviolet light . （通过在紫外线下照射可以使其内部信息快速消除）。
EEPROM(E2PROM)--electrically erasable, programmable ROM
The EEPROM is similar to an EPROM. In an EEPROM the erasure is done electrically by applying a special voltage to the chip.

70. Designing with ROM (P253)
To design a system using a ROM , you need only to have a list of miniterms for each function.
Example 4.7.1: Realize following functions using ROM .

71. The Structure and Capability for Memory (ROM and RAM)
words
n-to-2n
decoder
W2n-1
Address
inputs
Data outputs

72. Both AND array and OR array are programmable.
PLA（可编程逻辑阵列）
The most general type is the programmable logic array(PLA). In the PLA, the user specifies the all of the connections (in both AND array and OR array). Thus , we can create any set of sum of products expressions .
Both AND array and OR array are programmable.
F=A’B’+A’B+AB
=A’+B
G=A’B’+AB’=B’

73. Designing with PLA (P254-256)
Example 4.7.2: Consider the same example we used to illustrate the ROM and realize following functions using PLA .

74. 4.7.4 PAL (Programmable Array Logic 可编程阵列逻辑)
In a PAL the connections to the OR gates are specified(fixed); the user can determine the AND gate inputs. Each product term can be used only for one of the sums. Each output comes from an OR that has its own group of AND gates connected to it .
Programmable
Fixed

75. Design with PAL From the second K-map. We will get: W=AB’C’+A’CD+ACD
X=A’BC’+ACD’+A’CD+BCD
Y=A’C’D+ACD+BCD

76. From the second K-map. We will get: W=AB’C’+A’CD+ACD
X=A’BC’+ACD’+A’CD+BCD
Y=A’C’D+ACD+BCD
Read example 4.9

77. 4.8 Solving Larger Problem
4.8.1 sections will be read by student-self .
An error coding and decoding system(P268)
We are designing two systems that are to be used in conjunction with an error detection and correction scheme . We have 3 bits of information to be coded and transmitted. We will code these into 5-bit words, where the first 3 bits are just the information. The fourth bit is chosen such that there is an odd number of ones in bits 1,3,and 4. The fifth bit is chosen such that there is an odd number of ones in bits 2,3, and 5 .
Bit1 Bit2 Bit3 Bit4 Bit5
要设计两个系统，联合起来用来进行错误检测和校正．我们有３位数据需要编码并传输，将３位数据编码为５位数据，其中前３位代表了要传输的信息，第４位是使１，３，４位具有奇数个１．第５位的选择是使２，３，５位具有奇数个１．

78. We will design a decoder circuit that takes the 5-bit word (possibly containing an error)-call the bits a,b,c,d,e- and produces one of the words that it could have been- call the answer p, q, r. In addition, there are two outputs to indicate how sure we are that the answer is correct. Output f is 1 if the received word is the same as one of the transmitted,(that is no errors were made); and output g is 1 if the answer is the only data that could have resulted from no errors or a single error.
我们将设计一个解码电路获得5位字（可能包含有错误）-将这五位字叫 a,b,c,d,e. 解码电路产生3位信息位，叫做p,q,r. 同时，解码电路有两个输出用来显示对接受的数字其正确度有多么的确认。当接受到的数字和要传输的数字一致时（即没有错误），输出f为1，当接受的数字是由单个错误和没有错误引起的，则输出为1。

79. A block diagram of the system is shown below.
Transmission
media
coder
Decoder/
corrector z y x v w a b c d e p q r f g
Note: When the 5-bit words are transmitted, an error may occur during that transmission. Here, we will design the system under the assumption that at most one error occurs in a 5-bit word. An error results in one of the 1’s changing to a 0, or one of the 0’s changing to a 1.

80. Solution process: Section 1 : design coder with ROM
Step1: List the truth table of coder
Step2: realize the logic circuit with ROM
The description of coder
The fourth bit is chosen such that
there is an odd number of ones
in bits 1,3,and 4.
The fifth bit is chosen such that
there is an odd number of ones
in bits 2,3, and 5 .
truth table of coder
x y z v w

81. Section 2 : design decoder with ROM
When a 5-bit word is received, there are three possibilities.
First, no error:
If abcde=xyzvw then pqr=xyz, flag f=1,g=1
Second, a single error matches only one transmitted word:
If abcde= xyzvw=00011 then pqr=xyz, flag f=0, g=1
Finally, a single error could come from two or more different transmitted words :
If abcde= xyzvw=00011 or then p=x, q=0 or 1, r=z , flag f=0, g=0
x y z v w

82. Step1: List the truth table of coder
Step1: List the truth table of coder . Step2: realize the logic circuit with ROM
a b c d e p q r f g x x x x x
the truth table
x y z v w

83. 作业 10
用4选一数据选择器实现下列函数:
F(ABC)=∑(0,2,4,5)
F(ABC)= ∑(1,3,5,7)
F(ABCD)= ∑(0,3,12,13,14)