1. ECE 3450 M. A. Jupina, VU, 2012  Overview of Digital Logic Technologies  FPLD Technologies  Altera DE2 Development Board  Hardware Description Languages  Quartus II Software and Tutorial Field Programmable Logic Devices (FPLDs)

2. Some Key Lecture Objectives A discussion of how digital logic circuits can be implemented through various technologies (Discrete vs PLD vs ASIC vs Full Custom). Understand how FPLD technology is implemented by briefly looking at CPLD and FPGA architectures. Understand the advantages of FPLD technology. An overview of the Altera DE2 board and the Quartus II software. Course projects will use the Altera FPLD boards as a platform to implement complicated digital systems. With the Quartus II software, you will use a system design approach to create your designs. A brief (very brief) discussion of VHDL and the future of VHDL-AMS and mixed signal ICs. References: 1.Fundamentals of Digital Logic, Sections 2.9, 2.10, 3.5 – 3.7, and Appendices A-E. 2.Document files at the course web site ECE 3450 M. A. Jupina, VU, 2012

3. Digital Logic Technologies ECE 3450 M. A. Jupina, VU, 2012

4. A 7400-Series Chip Dual-inline package Structure of 7404 chip V DD Gnd ECE 3450 M. A. Jupina, VU, 2012

5. VDDVDD x 1 x 2 x 3 f 7404 74087432 Discrete Implementation Example ECE 3450 M. A. Jupina, VU, 2012

6. General Structure of a PLA f 1 AND plane OR plane Input buffers inverters and P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n ECE 3450 M. A. Jupina, VU, 2012

7. An Example of a PLA f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane AND plane P 3 P 4 ECE 3450 M. A. Jupina, VU, 2012

8. An Example of a PAL f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4

9. Structure of a CPLD PAL-like block I/O block PAL-like block I/O block PAL-like block I/O block PAL-like block I/O block Interconnection wires ECE 3450 M. A. Jupina, VU, 2012

10. A Section of a CPLD ECE 3450 M. A. Jupina, VU, 2012

11. Structure of a FPGA ECE 3450 M. A. Jupina, VU, 2012

12. Logic Block Example A two-input lookup table Complete Logic Block ECE 3450 M. A. Jupina, VU, 2012

13. A Sea-of-Gates Gate Array ECE 3450 M. A. Jupina, VU, 2012

14. An Example of a Logic Function in a Gate Array ECE 3450 M. A. Jupina, VU, 2012

15. A Simplified Floor Plan of a Standard Cells Based Design ECE 3450 M. A. Jupina, VU, 2012

16. Standard Cell Structure VDD VSS n tub p tub or substrate Intra-cell wiring pullups pulldowns  All cells have same pitch (height), may have different widths.  VDD, VSS (ground) connections are designed to run through cells.  A feedthrough area may allow wires to be routed over the cell. ECE 3450 M. A. Jupina, VU, 2012

17. Example: Full Adder Schematic Two Outputs: Sum and Carry sum carry x1 x2 n1 n2 n3 n4 ECE 3450 M. A. Jupina, VU, 2012

18. A Candidate Layout of a Full Adder x1x2n1n2n3n4 a b c s co Density = 5 ECE 3450 M. A. Jupina, VU, 2012

19. Layout of Full Adder Cell XOR XOR NAND NAND NAND NAND (2) (2)(2) (2) (2) (3) ECE 3450 M. A. Jupina, VU, 2012

20. Intel Pentium (IV) Microprocessor 2001 42 million transistors 2 GHz clock ECE 3450 M. A. Jupina, VU, 2012

21. Emerging Chip Architecture IP CORE FPLD Circuits Silicon Chip ECE 3450 M. A. Jupina, VU, 2012

22. Example of a System-on-a-Chip (SOC) Architecture System-on-a-Programmable Chip (SOPC) NOW EMERGING! ECE 3450 M. A. Jupina, VU, 2012

23. Digital Logic Technology Tradeoff ECE 3450 M. A. Jupina, VU, 2012

24. Comparison of Digital Technologies ECE 3450 M. A. Jupina, VU, 2012

25. FPLD Advantages 1.Re-configurable: The IC can be configured or “wired” to perform a particular task at a given instance in time and then reconfigured or “rewired” to perform another task a moment later. For example, the IC could be used as a low pass FIR digital filter one moment then reconfigured as a band pass FIR filter the next moment. 2.Rapid Prototyping 3.FPGA to ASIC Design (Example: Altera Stratix II to HardCopy II) http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp?f=hc2hp&k=m1 FPLD ROM ECE 3450 M. A. Jupina, VU, 2012

26. Complexity of Logic Element –How many inputs/outputs for the logic element? –Does the basic logic element contain a FF? What type? Interconnect –How fast is it? Does it offer ‘high speed’ paths that cross the chip? How many of these? –Can I have on-chip tri-state busses? –How routable is the design? If 95% of the logic elements are used, can I route the design? More routing means more “route-ability,” but less room for logic elements Issues in FPLD Technologies ECE 3450 M. A. Jupina, VU, 2012

27. Macro elements –Are there SRAM blocks? Is the SRAM dual ported? –Is there fast adder support (i.e. fast carry chains?) –Is there fast logic support (i.e. cascade chains) –What other types of macro blocks are available (fast decoders? register files? ) Clock support –How many global clocks can I have? –Are there any on-chip Phase Locked Loops (PLLs) or Delay Locked Loops (DLLs) for clock synchronization, clock multiplication? Issues in FPLD Technologies Continued ECE 3450 M. A. Jupina, VU, 2012

28. What type of I/O support exists? –TTL, CMOS are a given –Support for mixed 5V, 3.3V I/Os? 3.3 v internal, but 5V tolerant inputs? –Support for new low voltage signaling standards? GTL (Gunning Transceiver Logic) - used on Pentium II HSTL - High Speed Transceiver Logic SSTL - Stub Series-Terminate Logic USB - Universal Serial Bus (differential signaling) AGP - Advanced Graphics Port –Maximum number of I/O? Package types? Ball Grid Array (BGA) for high density I/O Issues in FPLD Technologies Continued (bottom view) ECE 3450 M. A. Jupina, VU, 2012

29. Examples of FPLDs and Advanced High Pin Count Package Types PLCC PQFP Ceramic PGA ECE 3450 M. A. Jupina, VU, 2012

30. Altera Max7000/Max7000A –EEPROM based, very fast (t p = 7.5 ns) –Basically a PLD architecture with programmable interconnect. –Max 7000A family is 3.3 V Altera Flex10K/10KE –LEs (Logic elements) have 4-input LUTS (look-up tables) and 1 FF –Fast Carry Chain between LE’s and Cascade chain for logic operations –Large blocks of SRAM available as well Altera FPLD Family Summaries ECE 3450 M. A. Jupina, VU, 2012

31. MAX 7000 Macrocell (36 signals from PIA) (16 inputs) Output can be fed back to input for state machine implementation ECE 3450 M. A. Jupina, VU, 2012

32. MAX 7000 LAB and PIA ECE 3450 M. A. Jupina, VU, 2012

33. MAX 7000 CPLD Architecture ECE 3450 M. A. Jupina, VU, 2012

34. FLEX 10K LE ECE 3450 M. A. Jupina, VU, 2012

35. FLEX 10K LAB and Interconnects ECE 3450 M. A. Jupina, VU, 2012

36. 8-Bit Parallel Adder Example ECE 3450 M. A. Jupina, VU, 2012

37. Product Term of Eight Variables Example ECE 3450 M. A. Jupina, VU, 2012

38. FLEX 10K FPGA Architecture ECE 3450 M. A. Jupina, VU, 2012

39. The Altera DE2 Development Board ECE 3450 M. A. Jupina, VU, 2012

40. In-System Programming of the Altera Development Board ECE 3450 M. A. Jupina, VU, 2012

41. Connections Between the Pushbuttons, the LEDs, and the Altera FPGA ECE 3450 M. A. Jupina, VU, 2012

43. Examples of Dedicated Pin-Outs on the DE2 Cyclone II Chip ECE 3450 M. A. Jupina, VU, 2012

44. Logic Synthesis: convert a description of a digital system in a Hardware Description Language (HDL) to an implementation technology. library ieee; use ieee.std_logic_1164.all; entity majority is port ( A, B, C : in std_logic; Y: out std_logic ); end majority; ARCHITECTURE a of majority is begin Y <= (A and B) or (A and C) or (B and C); end a; HDL description Gates Synthesis Logic Synthesis ECE 3450 M. A. Jupina, VU, 2012

45. VHDL is a language used for simulation and synthesis of digital logic. A VHDL description of a digital system can be transformed into a gate level implementation. This process is know as synthesis. VHDL for Combinational Logic ECE 3450 M. A. Jupina, VU, 2012

46. VHDL has a reputation as a complex language (it is!) We will use a small subset of the language for our purposes Some VHDL constructs: –Signal Assignment: A <= B; –Comparisons = (equal), > (greater than), < (less than), etc. –Boolean operations AND, OR, NOT, XOR –Sequential statements (CASE, IF, FOR) –Concurrent statements (when-else) VHDL Statements ECE 3450 M. A. Jupina, VU, 2012

47. Every VHDL model is composed of an entity and at least one architecture. Entity describes the interface to the model (inputs, outputs) Architecture describes the behavior of the model Can have multiple architectures for one entity (we will only use one in this class). VHDL Combinational Template ECE 3450 M. A. Jupina, VU, 2012

48. entity model_name is port ( list of inputs and outputs ); end model_name; architecture arch_name of model_name is begin concurrent statement 1 concurrent statement 2... concurrent statement N; end arch_name; All of the text not in italics are VHDL keywords. VHDL is NOT case sensitive. (ENTITY is same as entity is same as EnTiTy). A VHDL Template for Combinational Logic ECE 3450 M. A. Jupina, VU, 2012

49. library ieee; use ieee.std_logic_1164.all; entity example is port ( A, B, C : in std_logic; Y: out std_logic ); end example; -- this is the architecture declaration, uses only -- one concurrent statement. ARCHITECTURE a of example is begin Y <= (A and B) or (A and C) or (B and C); end a; Description Implementation A VHDL Example of an XOR Gate ECE 3450 M. A. Jupina, VU, 2012

50. Analog and Mixed Signal VHDL (VHDL-AMS) The IEEE 1076.1 language (VHDL-AMS) is a superset of the IEEE Std 1076-1993 (VHDL) that provides capabilities for describing and simulating analog and mixed-signal systems. VHDL-AMS was developed to provide the industry with a high-level design language to master future challenges in both mixed digital and analog system design as well as multi-physics applications. Currently, VHDL-AMS provides simulation only. Future software could provide synthesis. For example, field- programmable analog arrays (FPAA) are being developed. A FPAA containing many (~20) analog function blocks could be configured as DC level shifters, rectifiers, amplifiers, filters, oscillators, comparators, equalizers, etc. ECE 3450 M. A. Jupina, VU, 2012

51. FPAA Reconfiguration Example While FPAA technology is very young, and still expensive, it could someday be useful for creating communications products that would work on any standard. For instance, a cell phone with a re-programmable analog-to-digital converter would search the entire communications band for a signal, then grab the necessary program from memory to make itself into a code-division multiple access (CDMA), time-division multiple access (TDMA), or global system for mobile communications (GSM) phone. Such a phone could be used in Japan, Europe, or the US without modification. ECE 3450 M. A. Jupina, VU, 2012

52. VHDL-AMS Code Example -- VHDL-AMS model of an Analog Schmitt Trigger -- Description -- This Schmitt trigger uses a signal to model a simple hysteresis -- loop. When the input voltage exceeds the high threshold, the internal -- state switches to 5 Volts and when the input drops below the low threshold, -- the state switches to 0 Volts. -- The output is an ideal voltage source which contributes to the output -- terminal OutTerminal. -- LIBRARY DISCIPLINES; LIBRARY IEEE; USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL; USE IEEE.MATH_REAL.ALL; entity AnalogSchmitt is end entity AnalogSchmitt; architecture Hysteresis of AnalogSchmitt is TERMINAL n1,n2 : ELECTRICAL; ECE 3450 M. A. Jupina, VU, 2012

53. VHDL-AMS Example Continued -- declare a signal to memorize the hysteresis state: SIGNAL State : REAL := 0.0; -- initial state is low QUANTITY vin ACROSS iin THROUGH n1; -- declare a through branch for the output voltage source quantity vout across iout through n2; begin -- the architecture consists of two architecture statements: -- a conditional concurrent signal assignment to implement the hysteresis -- a simultaneous statement to implement the equation for the output source vin == 5.0 * sin(2.0 * math_pi*0.5E3*NOW); -- hysteresis: break State => 0.0 when Vin'above(1.0); -- trigger event when Vin > 1.0 break State => 5.0 when not Vin'above(2.4); -- trigger event when Vin < 2.4 -- output voltage source equation: vout == State'Ramp(1.0e-9,1.0e-9); -- the use of ramp assures that when a discontinuity -- in State arises, it is announced to the simulator end architecture Hysteresis; ECE 3450 M. A. Jupina, VU, 2012

54. Altera Quartus II Software ECE 3450 M. A. Jupina, VU, 2012

55. Required Installation of Quartus II on Laptops  Go to the Altera folder on the K:\ Drive. Download the executable file 91_quartus_free to your laptop’s hard drive. Install the Quartus II software.  After Installation, run the Quartus II software. Go to the menu Tools, License Setup, and in the box for License File put the following 5282@153.104.45.65 so that your laptop can find the license on the ECE server. ECE 3450 M. A. Jupina, VU, 2012

56. Design Process for Schematic or VHDL Entry ECE 3450 M. A. Jupina, VU, 2012

57. Create/Edit Schematic/VHDL Compiler repeat until no errors Create Simulation Waveforms Simulator Run simulation until functionally correct Timing Analysis? Modify design until timing specs are met Program Device Design Implementation Methodology ECE 3450 M. A. Jupina, VU, 2012

58. Creating a New Quartus II Project ECE 3450 M. A. Jupina, VU, 2012

59. Setting the FPGA Device Type The Cyclone II Chip resides on the DE2 Board. DE2 Cyclone II EP2C35F672C6 ECE 3450 M. A. Jupina, VU, 2012

60. Creating the Top-Level Project Schematic Design File ECE 3450 M. A. Jupina, VU, 2012

61. Selecting a New Symbol with the Symbol Tool ECE 3450 M. A. Jupina, VU, 2012

62. Active Low OR-Gate Schematic Example with I/O Pins Connected ECE 3450 M. A. Jupina, VU, 2012

63. Assigning Pins with the Assignment Editor ECE 3450 M. A. Jupina, VU, 2012

64. Active Low OR-Gate Timing Simulation with Time Delays ECE 3450 M. A. Jupina, VU, 2012

65. VHDL Entity Declaration Text ECE 3450 M. A. Jupina, VU, 2012

66. VHDL OR-Gate Model (with Syntax Error) ECE 3450 M. A. Jupina, VU, 2012

67. VHDL Compilation with a Syntax Error ECE 3450 M. A. Jupina, VU, 2012

68. Timing Analyzer Showing Input to Output Timing Delays ECE 3450 M. A. Jupina, VU, 2012

69. Floorplan View Showing Internal FPGA Placement of OR- Gate in LE and I/O Pins ECE 3450 M. A. Jupina, VU, 2012

70. ORgate Design Symbol ECE 3450 M. A. Jupina, VU, 2012

71. Implementation of a Simple Processor Data IE A IE B IE C Clock RARA RBRB RCRC IE X RXRX Multiplexer SYSY S DATA SASA SCSC SBSB ALU IE Y RYRY State Machine IE A IE B IE C SCSC S DATA SASA SBSB Done IE X IE Y AddSub SYSY Bus AddSub Start ECE 3450 M. A. Jupina, VU, 2012

72. Altera Implementation of Simple Processor ECE 3450 M. A. Jupina, VU, 2012

73. An Example Design Illustrating the Mapping of Multi-Bit Connections ECE 3450 M. A. Jupina, VU, 2012

74. An Example with a LPM Device ECE 3450 M. A. Jupina, VU, 2012

75. Lpm_counter0 MegaWizard Edit Window ECE 3450 M. A. Jupina, VU, 2012