1. Altera DE2 Board and Quartus II Software ECE 3450 M. A. Jupina, VU, 2014

2. Lecture Objective An overview of the Altera DE2 board and the Quartus II software. Course projects will use the Altera FPLD boards as a platform to implement complicated digital systems. With the Quartus II software, you will use a system design approach to create your designs. References: 1.Fundamentals of Digital Logic, Sections 2.9, 2.10, 3.5 – 3.7, and Appendices A-E. 2.Document files at the course web site ECE 3450 M. A. Jupina, VU, 2012

3. The Altera DE2 Development Board ECE 3450 M. A. Jupina, VU, 2012

4. In-System Programming of the Altera Development Board ECE 3450 M. A. Jupina, VU, 2012

5. Connections Between the Pushbuttons, the LEDs, and the Altera FPGA ECE 3450 M. A. Jupina, VU, 2012

7. Examples of Dedicated Pin-Outs on the DE2 Cyclone II Chip ECE 3450 M. A. Jupina, VU, 2012

8. Required Installation of Quartus II on Laptops  Go to the ECE3450 folder on the K:\ Drive. Download the executable file 91_quartus_free to your laptop’s hard drive. Install the Quartus II software.  After Installation, run the Quartus II software. Go to the menu Tools, License Setup, and in the box for License File put the following 5282@153.104.45.65 so that your laptop can find the license on the ECE server. ECE 3450 M. A. Jupina, VU, 2014

9. Design Process for Schematic or VHDL Entry ECE 3450 M. A. Jupina, VU, 2014

10. Create/Edit Schematic/VHDL Compiler repeat until no errors Create Simulation Waveforms Simulator Run simulation until functionally correct Timing Analysis? Modify design until timing specs are met Program Device Design Implementation Methodology ECE 3450 M. A. Jupina, VU, 2014

11. Creating a New Quartus II Project ECE 3450 M. A. Jupina, VU, 2014

12. Setting the FPGA Device Type The Cyclone II Chip resides on the DE2 Board. DE2 Cyclone II EP2C35F672C6 ECE 3450 M. A. Jupina, VU, 2014

13. Creating the Top-Level Project Schematic Design File ECE 3450 M. A. Jupina, VU, 2014

14. Selecting a New Symbol with the Symbol Tool ECE 3450 M. A. Jupina, VU, 2014

15. Active Low OR-Gate Schematic Example with I/O Pins Connected ECE 3450 M. A. Jupina, VU, 2014

16. Assigning Pins with the Assignment Editor ECE 3450 M. A. Jupina, VU, 2014

17. Active Low OR-Gate Timing Simulation with Time Delays ECE 3450 M. A. Jupina, VU, 2014

18. VHDL Entity Declaration Text ECE 3450 M. A. Jupina, VU, 2014

19. VHDL OR-Gate Model (with Syntax Error) ECE 3450 M. A. Jupina, VU, 2014

20. VHDL Compilation with a Syntax Error ECE 3450 M. A. Jupina, VU, 2014

21. Timing Analyzer Showing Input to Output Timing Delays ECE 3450 M. A. Jupina, VU, 2014

22. Floorplan View Showing Internal FPGA Placement of OR- Gate in LE and I/O Pins ECE 3450 M. A. Jupina, VU, 2014

23. ORgate Design Symbol ECE 3450 M. A. Jupina, VU, 2014

24. Implementation of a Simple Processor Data IE A IE B IE C Clock RARA RBRB RCRC IE X RXRX Multiplexer SYSY S DATA SASA SCSC SBSB ALU IE Y RYRY State Machine IE A IE B IE C SCSC S DATA SASA SBSB Done IE X IE Y AddSub SYSY Bus AddSub Start ECE 3450 M. A. Jupina, VU, 2014

25. Altera Implementation of Simple Processor ECE 3450 M. A. Jupina, VU, 2014

26. An Example Design Illustrating the Mapping of Multi-Bit Connections ECE 3450 M. A. Jupina, VU, 2014

27. An Example with a LPM Device ECE 3450 M. A. Jupina, VU, 2014

28. Lpm_counter0 MegaWizard Edit Window ECE 3450 M. A. Jupina, VU, 2014